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Reliability evaluation of Commercial off-the-shelf (COTS) processors against faults induced by radiation is a challenging problem. Some alternatives have been proposed to radiation test but they are very time consuming and lack of the observability needed. This work analyses the possibility to use an HDL model for estimating applications dependability on Texas Instruments MSP430 processor early in...
This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime...
Asynchronous circuits possibly have several potential advantages in comparison with synchronous one. In this paper, we attempt to introduce asynchronous circuit design method into the control unit of our 8-bit microprocessor by the burst-mode design method and implemented the asynchronous 8-bit microprocessor with outputs to observe all registers and the program counter by using a standard FPGA development...
In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process...
As it is known, the immune system found in biological organisms is robust and able to identify a large scale of diseases, infectious pathogens, or other harmful effects. Built on a huge cell-based structure in a well organized hierarchical mechanism, this system expresses remarkable self-healing, surviving and evolution abilities. The basic idea of the paper is to take inspiration of these mechanisms...
Emerging devices open the way to build nanoscale logic cells, dedicated to high-density reconfigurable computation. Nevertheless, in an architectural context, fine-grain logic cells integration is limited by traditional interconnection scheme and associated overload. This paper describes an interconnection scheme, based on static and incomplete interconnection topologies. We also propose a method...
Nowadays, Real-Time Operating Systems (RTOSs) are often adopted in order to simplify the design of safety-critical applications. However, real-time embedded systems are sensitive to transient faults that can affect the system causing scheduling dysfunctions and consequently changing the correct system behavior. In this context, we propose a new hardware-based approach able to detect faults that change...
This paper describes an interconnection scheme and its associated mapping method, used to program complex functions onto reconfigurable architectures, based on nanoscale logic cells. To interconnect such fine-grain logic cells, classical techniques are not suitable because of a large overhead. Therefore, we propose the use of static and incomplete interconnection topologies. We also propose a method...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an OpenRISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient,...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Designing dependable systems is a systematic task where area, power and performance are competing constraints. In many applications, design restrictions do not permit the total hardening of a design, leaving some internal circuitry vulnerable to radiation effects. Hierarchical analysis is necessary to identify the relative importance and vulnerability of individual sub-circuits in a design so that...
The paper deals through computer-aided modeling, numerical simulation and experimental research with the bio-inspired digital systems, in order to implement VLSI hardware which exhibits the abilities of living organisms, such as: evolution capabilities, self-healing and fault-tolerance. The theoretical backgrounds of the work are founded in cellular embryology's basic concepts. In the first stage...
Distributed generation (DG) from wind power becomes increasingly popular worldwide. However, the connection of large wind DGs onto existing radial distribution feeders cause challenges on proper operations of both DGs and their connected feeders. This paper proposes a new Network-enabled Adaptive Protection and Control (NAPC) strategy for properly interfacing wind DGs into distribution grids. The...
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