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This paper describes a concept of Field Programmable Neural Networks (FPNNs) for artificial neural networks implementation in FPGAs, presents a model of fault tolerant FPNNs and different fault tolerance improving techniques based on the model. It describes an experiment based on one of these techniques and presents its results.
This paper introduces a set of methods for mapping the trained neural networks into the lighted grid structured Field Programmable Neural Networks without the use of a training data set. These methods use information obtained from original neural networks such as a network structure, connection weights and biases. The principles of these mapping methods are described and the used grid FPNNs are explained...
For various types of applications, it is necessary to guarantee maximal level of fault tolerance and high reliability of components, avionic and railway applications can serve as an example of these applications. In these devices, electronic components are exhibited to the environment conditions, from among them especially cosmic radiation can have an undesired and destructive effect. In this paper,...
As the speed of current computer networks increases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is...
In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting...
In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First, the principles of test platform based on an external SEU injector are presented; all components of test platform and their role during SEU simulation are described. Then, a recovery...
Many algorithms and hardware architectures are proposed to increase processing speed of time-critical operations in the field of longest prefix matching, packet classification and regular expression matching. Despite this fact, there is still no free and easily extensible platform for evaluation, comparison and experiments with existing approaches. We propose the Net bench Framework which aims to...
In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bit stream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require...
In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process...
Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration...
With the increased amount of data transferred by computer networks, the amount of the malicious traffic also increases and therefore it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. Pattern matching is the time critical operation of current IDS. This paper deals with the analysis of regular expressions...
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