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The paper presents a 24 V chopper offset-stabilized operational amplifier with symmetrical RC notch filters, having a 4–24 V supply range, and being realized using a 0.25 ßm BCD process. The amplifier has a typical offset voltage of 1.2 μV, a minimum PSRR of 128 dB, a minimum CMRR of 120 dB, a minimum open-loop gain of 134dB, a noise PSD of 30 nV/√Hz, 1.8 MHz unity gain bandwidth, and THD + noise...
A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with...
Power Management Integrated Circuits (PMIC) chips contain large power switches - usually LDMOS transistors, along with low current control circuitry. During transistor switching, charge carriers are injected into the substrate and affect the surrounding devices. In junction isolated technologies, hole injection is effectively suppressed using highly doped n-type layers, while electron injection requires...
In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.
Radiation induced soft errors are a serious concern not only for memories but also logic circuits. Amongst the several proposed countermeasures, Bulk Built-in Current Sensors represent a promising approach with fast response times and reasonable costs in terms of area and power. However, these circuits, as well as similar sensors that measure substrate effects, are strongly susceptible to substrate...
Noise parameter measurements of six candidate transistors for a Square Kilometer Array (SKA) low-noise amplifier (LNA) are presented. They provide reliable data in the frequency range where some low-noise transistors are inadequately characterized. The results of these measurements inform the design of an LNA for SKA1-Survey Band 2 with measured minimum noise temperature of 21 K.
This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments...
In biomedical field there is a great need of VLSI in designing integrated bioamplifier circuits which performs the operation of amplifying low amplitude and low frequency signals. Due to excessive demand of implantable and wearable devices for processing biopotential signals, a low power bioamplifier is proposed in this paper and power dependency of bioamplifier on different current mirror configuration...
Low noise amplifier is designed at 2.1GHz and 4.6GHz. Matching network is designed using lumped elements. Frequency transformation technique is employed to synthesis lumped element. Stabilization circuit is included for stable LNA throughout frequency range. Simulation result gives gain of 12.03dB and 10.16dB and NF of 0.5818dB and 1.2dB respectively at 2.1GHz and 4.6GHz. Input and output VSWR is...
In this paper, we propose Joint SRAM (JSRAM) cell, a novel circuit-level hardening solution for having a flexible trade-off between cache capacity and reliability. Our solution aims at addressing both permanent and transient faults in SRAM cells. JSRAM technique enhances read-stability by increasing critical Read Static Noise Margin (RSNM) to decrease faults when circuit operates at lower VDD voltages,...
This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a...
The level of requirements for a readout front-end electronics dedicated for X-ray imaging applications, such as: high count rate ability of input pulses, low noise, low power dissipation and low silicon area occupation noise, is still increasing. The question: what one can do to minimize silicon area and keep front-end electronics analog parameters at a desirable level at the same time, is still important...
Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed...
This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (< 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for...
Noise canceling techniques have been successfully applied to the design of modern multi-band RF-CMOS inductor-less receivers. However, low voltage supply requirements are imposing new design challenges which are pushing the operation of the MOS transistor into moderate or weak inversion, making the setup of closed sizing expressions a difficult task. This paper presents a Si2 OpenAccess based circuit...
This paper presents a novel power-constrained algorithmic design methodology for radiofrequency (RF) low-noise amplifiers (LNAs). The methodology is based on matrix descriptions of the transistors allowing for the first time the derivation of exact synthesis equations for input impedance matching and transducer gain optimization. The equations are embedded in an algorithm for design tradeoffs between...
In this paper a voltage differentiator based on OTA-C structure is introduced. To maintain a large time constant for biological signal processing at pico farad range filter capacitor, the input voltage attenuator is applied to reduce the overall transconductance gain of this OTA. This OTA-C voltage differentiator is simulated on a standard CMOS 0.35µm process and operated at 1.2 V with 4.8 nW power...
In this paper, a wide-band fully differential linear low noise amplifier (LNA) in a standard 130nm CMOS process is presented. The LNA utilizes Active Post Distortion (APD) as a voltage combiner that prepares a linear transconductance for enabling harmonic cancellation, which can also mitigate the impedance matching device noise. The impedance matching device is connected to the output transistors...
The performance of logic function could be affected significantly by the noise effect as the dimension of CMOS devices scales to nanometers. Thus, many pertinent researches about noise-tolerant logic gate have received growing attention. Considering the randomness as the noise's nature, probabilistic-based approach proves better noise-immunity and three design schemes with the technique of Markov...
This paper presents a novel two-step pixel-level analog-to-digital converter (ADC) design, which is embedded in a 17μm-pitch pixel for Infrared Focal Plane Array (IRFPA). Digitization includes two successive steps: the first is reciprocal and the second linear. With the reciprocal conversion, a high dynamic range is achieved, and the linear conversion, on the other hand, guarantees a suitable frame...
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