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Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed...
In this paper, we propose the design and development of verification IP (VIP) of STBUS, a widely used bus protocol from STMicroelectronics [1]. VIP is a standalone, pre-verified and built-in verification infrastructure, which can be easily plugged in the simulation-based tests. We have followed Universal Verification Methodology (UVM) for the modelling of the STBUS VIP. Firstly we have verified the...
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