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Single and multi-voids position effects will be highlighted from an electrothermal viewpoint. Complementary numerical investigations will show that these effects are strongly dependent on the properties of the backside metallization of the MOSFET chip. The methodology based on a coupled analysis of electrothermal modeling and experiments that led to these conclusions will be detailed.
This paper presents buckled nitride thin-film encapsulation using anti-adhesion layer assisted transfer technique and BCB/nitride bilayer wrinkling due to elastic property mismatch between the two attached materials. A 900 nm silicon nitride film is deposited on a Si carrier wafer coated with hydrophobic monolayer and then non-patterned nitride film is directly bonded to BCB sealing rings prepared...
This paper is on a vertical through silicon via (TSV) fabrication method of integrated circuit (IC) packages. The vertical TSV processes are developed by evaluating different via depth and diameter. The stress simulation and analysis of the as-formed vertical TSV structure are also conducted to predict the possible mechanical failure during the reliability test.
Fan-out wafer-level-packaging (FO-WLP) technology gets more and more significant attention with its advantages of small form factor, higher I/O density, cost effective and high performance for wide range application. However, wafer warpage is still one critical issue which is needed to be addressed for successful subsequent processes for FO-WLP packaging. In this study, methodology to reduce wafer...
Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the...
Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the...
During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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