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In this paper, we propose a reconfigurable architecture for discrete cosine transform (DCT) computation. The objective of the paper is to integrate the DCT computation in a complete embedded system based on ARM processors. Based on dynamic partial reconfigurable FPGAs, different versions of DCT computation are used to give adaptability and flexibility to the architecture. These adaptability responses...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
With the growing diversity of malware, researchers must be able to quickly collect many representative samples for study. This can be done, e.g., by using honeypots. As an alternative to software-based honeypots, we propose a singlechip honeypot appliance that is entirely hardware-based and thus significantly more resilient against compromising attacks. Additionally, it can easily keep up with network...
MPI is the traditional paradigm to parallelize applications for High Performance Computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in FPGAs. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx...
This paper focuses on the implementation and performance analysis of a hardware/Software implementation of a Object Request Broker (ORB) to support a network of Distributed Smart Camera (DSC) systems. We present the overall system architecture as a part of the whole System on Chip (SoC) within FPGA. The performance analysis performed on a software as well as on our hybrid implementation is explained...
Malicious software has become a major threat to computer users on the Internet today. To combat it, security researchers need to gather and analyze many samples to develop proper defense mechanisms. The setting of honeypots, which emulate vulnerable applications, is one method of gathering attack code. In contrast to the conventional software-based honeypots, we have proposed a dedicated hardware...
This paper presents an educational platform for digital system practices with a conventional PCI bus interface, based on reconfigurable hardware especially useful for the designing of hardware accelerators and systems with a PCI bus interface. The aim of the platform is to provide students with a single tool to develop rapid prototypes that covers all aspects involved in the study of digital systems...
We present an infrastructure for dynamic reconfiguration of heterogeneous coarse-grained reconfigurable architectures (CGRAs) based on our Gannet SoC platform. We introduce the infrastructure and in particular its domain-specific high-level programming language Gannet-C and discuss the language features that support dynamic reconfiguration and the way they are supported by the compiler and the hardware...
Extending the idea of preemptive multitasking to DPRS (Dynamic Partial Reconfiguration Systems) has far-reaching implications as many mechanisms supporting the concept, such as context saving and restoring, have to be built practically from scratch. This paper addresses previously neglected issues, related to design of effective preemption mechanisms for Flip-Flop-based and RAM-based hardware tasks...
In the field of microprocessors, speeds of processor doubles in every 18 months as, new microprocessors are always being designed using more and more advanced features. So, it's always a challenge to design a new microprocessor with faster execution speed. In this paper microarchitecture of superscalar processor is to be designed using VLSI. This Proposed design is based on the rigorous research done...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
This paper presents a PCI-Express based platform for the analysis and evaluation of designs that combines Triple Modular Redundancy and Dynamic Reconfiguration to provide Fault Tolerance and Self-repairing capabilities. The paper presents the general architecture of the platform and exemplifies its functionality with the implementation of a Self-Repairing CAN Gateway.
This paper describes implementation of Web server using Altera Nios II embedded IP core, a configurable general purpose embedded RISC processor with embedded peripheral architecture. A Web server is a computer that delivers Web pages to other computers in the network. Every Web server has a unique IP address and possibly a domain name. Any computer can work as Web server by installing server software...
An instance of measuring node of service life measuring and control system of household appliances using FPGA and nRF2401 is present. FPGA is the core of the system which is embedded with E-MAC IP core to realize the remote monitor system replying on the TCP/IP communication protocol, and nRF2401 is wireless periphery that realizes the wireless data acquisition. How to design and implement the hardware...
Recent trends show an increasing number of weblabs, implemented at universities and schools, supporting practical training in technical courses and providing the ability to remotely conduct experiments. However, their implementation is typically based on individual architectures, unable of being reconfigured with different instruments/modules usually required by every experiment. In this paper, we...
The dynamic reconfiguration technique based on FPGA (field-programmable gate array) can improve the resource utilization. The dynamic reconfiguration principles and methods are discussed. A remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet PHY (physical layer transceiver) is proposed. The hardware of system is designed with Xilinx Virtex-IIXC2V30P FPGA that embeds...
Run-time partial reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use direct memory access (DMA), master (MST) burst, and a dedicated block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA...
We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power...
In this paper we present a FlexPath network processor implementation, a platform with flexible, reconfigurable processing paths for packet processing. The path decision is made in hardware based on a packetpsilas network application. Packets may be processed by a CPU or even completely in hardware. With our demonstrator the performance of different processing paths is shown for a scenario with simple...
In this paper an idea is proposed, how to simulate a large digital system that could not be mapped onto single FPGA, utilizing the sate-of-the-art features of modern reconfigurable devices. Partial reconfiguration of these devices is the feature for the idea described. Methodology of design flow to any platform is proposed and main problems concerning this methodology are highlighted.
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