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For critical aerospace applications that experience a high intensity of single event upsets, the cache of a processor has to be protected against soft errors. This poses a challenge for cache design, since implemented redundancy causes timing and performance degradation of a processor. Sound design decisions should be made based on evaluations at every design stage. In this paper we present a platform-oriented...
A central issue in designing complex networked systems for critical applicative domains is the possibility of keeping each node of the network synchronized with respect to a given reference system time scale. The problem is even more critical when the synchronization accuracy determines directly the performance of a whole system or service. In this chapter a distributed synchronization infrastructure...
As CMOS technology scales into the nanometer era, future shipped microprocessors will be increasingly vulnerable to intermittent faults. Quantitatively characterizing the vulnerability of microprocessor structures to intermittent faults at an early design stage is significantly helpful in balancing system reliability and performance. Prior researches have proposed several metrics to analyze the vulnerability...
This paper proposes concepts of operation characteristics and support characteristics from the system mission need point of view and analyzes relationships between them. Definition, composition, content and requirements of system supportability objectives are put forward. This paper also researches methods for identifying system supportability objectives, including but not limited to use study, mission...
To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate...
Today's process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
In this paper we motivate the explicit validation of hold-time violations in silicon and propose a method for doing so. New hold-time failure model and test pattern generation methodologies are defined. We outline conditions under which these tests can be applied reliably. We present results of applying these test patterns on a microprocessor and discuss the implications of intermittent failures on...
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