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This paper presents a predictive SPICE model for the radiated ElectroMagnetic Interferences (EMI) of a 32-bit microcontroller. The aim of this work is to be able to predict, during the design stage, the level of electromagnetic emissions in order to establish pinout, design or layout rules. This model is intended to represent the EMI behavior of a microcontroller when it is running in a noisy mode...
A high efficiency power management system for solar energy harvesting applications is proposed. The power management system receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V~0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. The great voltage varieties...
This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal...
The following topics are dealt with: CMOS devices and technology; flash memory; semiconductor devices; MEMS; solid-state devices; and nanoelectronic devices.
As the performance gap between the CPU and the HDD has increased over time, NAND Flash based Solid State Drive (SSD) has emerged as an ideal candidate to fill this space. While continued cell scaling will further solidify the position of the NAND Flash in the compute applications, eventually it will hit a scaling wall creating opportunities for other types of memories. The vision for such a future...
In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65 nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the flash cell and the related HV MOS and the results...
The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (magnetoresistive random access memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which...
Vulnerability of a variety of candidate spacecraft electronics to total ionizing dose and displacement damage is studied. Devices tested include optoelectronics, digital, analog, linear bipolar devices, and hybrid devices.
As performance gains from scaling silicon slow, improvements in system performance must come from tighter integration. Proximity communication (PxC) enables designers to aggregate multiple chips that perform as a single large piece of silicon. PxC enables the heterogeneous integration of an optimized mix of process technology and functionality, such as DRAM, flash memory, and CMOS processor chips...
Impulse radio ultra-wideband (IR-UWB) proved to be a strong candidate for energy-efficient communication and ranging, resulting in multiple low-energy IR-UWB implementations. Current state-of the art publications however only realize parts of a complete IR-UWB RX system, lacking either a digital back-end (DBE), an analog front-end (AFE) and/or algorithms for synchronization and ranging. A 110 pJ/pulse,...
In this paper we present a low cost fault-tolerant attitude determination system to a scientific satellite using COTS devices. We related our experience in developing the attitude determination system, where we combine proven fault tolerance techniques to protect the whole system composed only by COTS from the effects produced by transient faults. We detailed the failure cases and the detection, reconfiguration...
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
RTS noise is a growing issue in flash memory as the cell size scales down. By investigating NMOS and Ring devices, it is shown that noise induced by the STI edge dominates cell RTS/noise with scaling or after cycling. Device 1/f characterization highlights the drain STI edge as a critical area for RTS improvement in flash.
A low leakage voltage pulse generator as needed in small non-volatile memories for RFID applications is presented. The voltage regulation loop is based on a capacitive divider which saves the static current usually consumed in a conventional pulse generator based on a resistor divider. The proposed generator has been used in a 64 bytes flash memory embedded in a RFID IC fabricated in a 0.22 mu CMOS...
When the thickness of tunnel oxide layer is thinner than 7 nm, the defects of tunnel oxide will form the leakage path easily. The trapped charges in trapping layer leak out through the leakage path and let we read the wrong data information. Therefore, the novel oxynitride process has been proposed to improve the reliabilities of flash memory by reducing the interface states and bulk defects. Moreover,...
Deposition of silver nano-particles (Ag-nps) in a thin aluminum oxide layer resulting in an increased frequency dependent dielectric constant has been investigated for possible applications in nano-FLASH memory and nano-CMOS devices. The design of nano-FLASH memory with embedded Ag-nps in the gate oxide has been analyzed through simulation that demonstrates the charge storage capability of Ag-nps...
This paper describes a low power and high performance camera signal processor system-on-a-chip (SoC) architecture for mobile camera applications such as the mobile phone, the personal digital assistant (PDA), and the personal multimedia player (PMP). In this work, we presented the use of the gated clock approach to reduce power consumption. The area of this chip is 2.8 mm times 2.7 mm and it was fabricated...
A 0.35 mum double-poly CMOS 16 b SAR A/D converter uses self-calibration techniques to obtain frac12 LSB INL. The differential and single-ended THD at 1Msample/s are 101dB and 96 dB, respectively. Each ADC consumes 20 mW at 3 V and occupies 2.9 mm2 active area, resulting in a 0.9 pJ/b FOM. The chip includes 3 ADCs, 2 DACs, 8051-microcontroller, CAN controller, DMA controller, 64 K flash memory and...
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