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Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on cryptography, we are investigating a different approach that is not adding extra silicon area: We study to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA...
System-on-Chips which include FPGAs are important platforms for critical applications since they provide significant software performance through multi-core CPUs as well as high versatility through integrated FPGAs. Those integrated FP-GAs allow to update the programmable hardware functionality, e.g. to include new communication interfaces or to update cryptographic accelerators during the life-time...
In this paper a random number generation method based on a piecewise linear one dimensional (PL1D) discrete time chaotic maps is proposed for applications in cryptography and steganography. Appropriate parameters are determined by examining the distribution of underlying chaotic signal and random number generator (RNG) is numerically verified by four fundamental statistical test of FIPS 140-2. Proposed...
As the security is becoming more and more important these days, we still should not forget about reliability. When designing a cryptographic device for some mission-critical or another reliability demanding system, we need to make the device not only attack-resistant, but also fault-tolerant. There are many common fault-tolerant digital design techniques, however, it is questionable, how these techniques...
In this paper, we propose a novel programmable processing element (PPE) for various cryptographic systems that can be used in IoT applications. The design enables the programmability, thus supporting a wide range of bit-widths (such as 16, 32, and 64). It employs a very long instruction word (VLIW) architecture with an instruction set and memory hierarchy specialized for crypto-processing. Both FPGA...
In this work, we propose a novel basic element called delay chain feedback loop (DCFL) to generate metastability. Using 16 DCFLs with different delay chains, a new digital true random number generator (TRNG) is constructed. The new TRNG has been implemented on Altera Cyclone II and Altera Cyclone IV FPGAs. The experimental results show that the TRNG is true random which can pass both the NIST and...
This work presents the proof of concept implementation for the first hardware-based design of Moving Target Defense over IPv6 (MT6D) in full Register Transfer Level (RTL) logic, with future sights on an embedded Application-Specified Integrated Circuit (ASIC) implementation. Contributions are an IEEE 802.3 Ethernet stream-based in-line network packet processor with a specialized Complex Instruction...
In confidential data transmission data security is an important factor. Advance Encryption Standard is symmetric cryptography standard used for confidential data transmission. However, some faults are injected during implementation of AES to reduce its reliability and may cause information leakage. Fault detection scheme includes the details of each transformation in AES algorithm. Simulation results...
Secrecy in communication is critical for people that have sensitive information. Steganography is a field that secures sensitive information by hiding it inside media files (such as images). What makes the concept of steganography powerful is that the secret message is hidden cleverly within the media file and thus carried around invisibly. Our paper proposed an automated method to secure a message...
In this paper we present an extended fault injection approach to configuration memory of SRAM-based FPGAs consisting of inter frame many bits upsets to be used as an evaluation tool for attack detection capability and countermeasure effectiveness in security sensitive design modules. The work presented in this paper is twofold. First, we present the concept of a fault detection mechanism for SRAM-based...
The cryptographic KECCAK algorithm has been developed by the circuit architect with the objective to enhance the design performances from frequency, throughput, efficiency, power consumption and area viewpoint of. The cryptographic KECCAK algorithm is implemented in many cryptographic circuits to ensure security. It is become the standard algorithm used to ensure the information integrity in numerous...
Exponentiation in multiplicative groups is the most time-consuming and critical operation for implementing asymmetric cryptography for key exchange, digital signatures, and digital envelopes in security protocols. Most of the designs previously reported to support this operation are mainly devoted to achieve the highest performance. However, in current computing paradigms highly dominated by interconnected...
Embedded System Reconfigurability has begun since few years thanks to the FPGA capabilities. Many approaches and methodologies have been adopted in literature. Several tools were proposed to designers, but a big luck of efficiency has been noticed. So several works studied this concept and still looking for the best tools and flow. This paper presents an overview of Reconfigurability concepts and...
In the last few decades, hardware-based embedded system incorporated with millions of logic gates; memory of megabytes size; high-speed processor and transceivers used for numerous applications such as industrial control, signal processing, communication infrastructure, etc. As the application data are massive and complex, it needs to be secured from adversary attack. In this context, a dynamic hash...
In this paper, we are targeting Altera Cyclone IV FPGA family to design an efficient GCD (Greatest Common Divisor) coprocessor based on Euclid's method with variable datapath sizes. The design was synthesized using seven chip technologies in terms of maximum frequency and critical path delay of the coprocessor. As a result, the comparison between different FPGA devices shows that Xilinx devices XC7VH290T-2-HCG1155...
This paper proposes a new approach for 32 bit Arithmetic and Logic Unit for multifunctional processors. The proposed ALU has a novel instruction set including Parity checker, Parity Generator, Binary to Gray converter, gray to binary converter and Manchester encoder decoder along with conventional ALU operations. This extended ALU caters the need of cryptographic processors where an extended security...
Internet of things (IoT) is communication between smart objects and human. It finds enormous applications in the field of healthcare monitoring, information management system, agriculture, predicting the natural disaster etc. In all those applications of IoT, security plays a vital role. In this paper, a study on various encryption light weight techniques used for IoT was analyzed. Also the performance...
SAKURA-G (Side-channel AttacK User Reference Architecture — G) board equipped with two Spartan-6 FPGAs was developed for physical attack experiments against a cryptographic circuit as a successor to SASEBO-GII. In this work we developed a clock manipulator for SAKURA-G, which generate glitch noises to provoke malfunctions on a cryptographic circuit. By using the DCM (Digital Clock Manager) and PLL...
In the paper, we propose a new method of modular multiplication computation, based on Residue Number System. We use an approximate method to find the approximate method a residue from division of a multiplication on the given module. We substitute expensive modular operations, by fast bit right shift operations and taking low bits. The carried-out simulation on Kintex7 XC7K70T board showed that the...
This article describes the implementation of Twofish — one of the Advanced Encryption Standard (AES) finalists, in Field Programmable Gate Array — FPGA. The core was implemented in Altera Quartus Cyclone board, is totally portable and can be used in any FPGA family. It was developed using the VHDL patterns. The algorithm was implemented for 128-bit word and key. The main goal of this work was the...
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