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As transistors decrease its size due to scaling, digital circuit capabilities increase. These increases are evident in terms of area, power, and speed. Due to the small nature of these devices, introducing parallel paths further increases functionality. Certain characteristics of FPGAs provide alternatives to achieve these improvements in a similar fashion. Partial reconfiguration(PR) further improves...
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
According to the characteristic of large space manipulator, an on-board real-time singularity detection design is proposed. On the basis of forward and inverse kinematics calculation, the forward and inverse power method is applied to obtain the singularity by iterative computation. Firstly, the 7-DOF manipulator kinematics model is described and analyzed, and the main computational process is presented;...
RADAR, an acronym for Radio Detection and Ranging, is used for various purposes both military as well as civilians. A fire-control radar (FCR) is specifically designed radar to provide information (mainly target azimuth, elevation and range) to a fire control system in order to calculate a firing solution (i.e. information on how to direct weapons such that they hit the target(s)). This Paper mainly...
SRAM-based FPGAs like Xilinx Virtex FPGA offer the highest processing capability currently available as radiation tolerant space qualified parts. However their configuration memory is not radiation hardened, monitoring and correction of configuration is required to prevent upsets from affecting operation. This paper presents a setup in which a controlling processor has access to the configuration...
Wireless open access research platform is one of the latest trend in the field of programmable hardware. It's reference library is openly accessible whereas hardware is believed to be of high performance. This platform can be used for designing and implementing state of the art wireless systems from basic elements to the end user level. WARP board houses a VIRTEX-7 Field programmable gate array. Software...
Through analyzing the small UAV (Unmanned Aerial Vehicle) flight control system based on CAN (Controller Area Network) bus, the paper focuses on the study of flight control system bus architecture, and puts up an ADS-B (Automatic Dependent Surveillance-Broadcast) architecture design which is suitable for this type of UAV. Transplants the mature ADS-B system with a focus on the design of CAN bus interface,...
In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is dequate for control tasks, which require decision making that could not easily be implemented in an application specific...
This paper is dealing with ways of configuration of the FPGA devices and time parameters of various types of configurations. Time model of configurations and reconfigurations has been designed. Outputs of the designed model are times of configurations, reconfigurations and partial reconfiguration derived from technical parameters of devices and from length of bitstreams.
The circuit of the signal acquisition module was designed and accomplished based on 24 high-precision A-E type serial A/D conversion chip ADS1258, employed Xilinx xc3s2000 FPGA as acquisition controller embedded in the chassis of N1 Compact-RIO, and host-programmed by Labview. The module achieved 16 Single-Ended input-channels with up to 23.7kHz (maximum) analog signal acquisition sampling rate. In...
We describe the design and performance of the GRAPE-MPs, a series of SIMD accelerator boards for quadruple/hexuple/octuple-precision arithmetic operations. Basic design of GRAPE-MPs is that it consists of a number of processing elements (PE) and memory components which handle data with quadruple/hexuple/octuple-precision. A GRAPE-MPs processor is implemented on a structured ASIC chip and an FPGA chip...
The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into...
Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network...
A compact implementation of a foreground segmentation processor in a multi-resolution transform domain has been proposed for HDTV signals. The proposed architecture is designed to simplify system controls by the hardware streaming and to reduce required memory capacities. It enables flowing pixels through all functional units in order, including multi-resolution spatial transform and temporal segmentation...
This paper proposes a design of multi protocol asynchronous serial communication M module, which can be configured as 8-channel RS-232 or 4-channel RS-422/485, and each channel's property including baud rate, character-bit, parity mode and stop-bit can be configured separatly through the software. FPGA is adopted as the development platform, using the Verilog HDL to design timing logic of Mbus interface,...
The embedded Ethernet is widely applied, and its research is very important. In this paper, the embedded Ethernet controller is designed. The Ethernet MAC sublayer protocol and the architecture of Ethernet data frame are briefly introduced. The 10/100Mbps adaptive Ethernet controller is designed with Verilog-HDL, which includes the WISHBONE bus interface, Tx/Rx module, flow control module, etc. The...
This paper proposes a high speed serial data acquisition scheme. The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition, and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS. This design shortens the design processs, simplifies the circuits, and...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
In this paper, we propose a programmable string matching architecture to process multiple characters at a single cycle. To simplify the architecture of the previous works, we employ a method of realigning the input data stream by offsets. We show that some registers can be eliminated by using the method. Additionally, we present two different approaches to implement a programmable hardware for string...
To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing clock speed is not viable due to heat dissipation and power consumption constraints. Hence Instead of trying to increase the clock speed, multi-core processor architectures with the lower frequency can be used...
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