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As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
This paper proposes a design of multi protocol asynchronous serial communication M module, which can be configured as 8-channel RS-232 or 4-channel RS-422/485, and each channel's property including baud rate, character-bit, parity mode and stop-bit can be configured separatly through the software. FPGA is adopted as the development platform, using the Verilog HDL to design timing logic of Mbus interface,...
This paper proposes a high speed serial data acquisition scheme. The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition, and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS. This design shortens the design processs, simplifies the circuits, and...
In this paper, we propose a programmable string matching architecture to process multiple characters at a single cycle. To simplify the architecture of the previous works, we employ a method of realigning the input data stream by offsets. We show that some registers can be eliminated by using the method. Additionally, we present two different approaches to implement a programmable hardware for string...
Extending the idea of preemptive multitasking to DPRS (Dynamic Partial Reconfiguration Systems) has far-reaching implications as many mechanisms supporting the concept, such as context saving and restoring, have to be built practically from scratch. This paper addresses previously neglected issues, related to design of effective preemption mechanisms for Flip-Flop-based and RAM-based hardware tasks...
The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine. Applicability and advantages of the proposed methods are confirmed through numerous examples of the designed hardware circuits that have been analyzed and compared. The results of experiments and FPGA-based...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
This paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) Instruction Set Architecture (ISA), capable of supporting reconfigurable operations as well. The VEX architecture supports up to 64 multiported shared...
Revolutions in the domain of computing have molded the structures and characteristics of computing systems. Conventional computing techniques involved the use of application specific integrated circuits to achieve a high performance at the cost of extremely inflexible hardware design meanwhile the flexibility of hardware design was achieved at the cost of slow speed processing by using programmable...
Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. In our approach to mitigate this problem, the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into...
Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reconfiguration, which is provided by several FPGA families...
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