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In previous generations of Intel FPGAs, we employed design separation through the use of LogicLock in Cyclone IIILS and Arria V devices. In the past, this meant separation of design elements as well as designated protected design boundaries in different ‘Logic Lock’ regions. Though separated logically, these regions have the same protection and risk if the key is revealed. Today, using Partition-Based...
SM4 is a 128-bit block cipher used in the WAPI (Wireless LAN Authentication and Privacy Infrastructure) standard for protecting data packets in WLAN. This paper proposes a novel method of CPA (Correlation Power Analysis) on SM4 based on chosen-plaintext. Using SM4 as target algorithm, Sakura-G FPGA board as hardware verification platform, we only collect 1000 power consumption waveforms to obtain...
Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption...
Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing...
With the rapid increase in computing and communication devices the need for security services has become crucial in information transfer. Protecting the digital information against security attacks is extremely important. Encipherment is the security mechanism that provides authenticity and confidentiality. In this paper a highly secured design for offline speech communication is presented. The proposed...
Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs -- the Xilinx Virtex-6...
Message verification is important for information security, and the hash-based algorithm is a kind of implementation method. In this paper, we propose a circuit implementation scheme to realize message verification, which is based on SHA1, called HMAC-SHA1. In our scheme, the MD5 circuit module is reusable such that the circuit size is reduced and the processing speed is improved. Finally, we use...
Reconfigurability is a unique feature of modern FPGA devices to load hardware circuits just on demand. This also implies that a completely different set of circuits might operate at the exact same location of the FPGA at different time slots, making it difficult for an external observer or attacker to predict what will happen at what time. In this work we present and evaluate a novel hardware implementation...
The Advanced Encryption Standard is the recent data security standard referred to as Federal Information Processing Standard 197 (FIPS 197) acquired worldwide by several private and public sectors for protective needs of data storage and secure data application from mobile consumer products to high end user. Most of the AES implementation for reconfigurable devices, however based on the configurable...
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources...
Embedded processors are an integral part of many communications devices such as mobile phones, secure access to private networks, electronic commerce and smart cards. However, such devices often provide critical functions that could be sabotaged by malicious entities. The supply of security for data exchange on basis of embedded systems is a very important objection to accomplish. This paper focuses...
In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is combined with a 32-bit general purpose 5-stage pipelined MIPS processor. The AES module used in this paper is fully pipelined. The processor fetches an instruction from the instruction memory and sends it to the decode stage. If the instruction is the crypto instruction...
The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data...
This paper presents the implementation and integration the AES 128 data encryption IP and the I2C serial communication interface IP, into the IP of the M8051 microcontroller. We detail each block and validate them though testbench simulation. We performed functionality testing in FPGA to verify the correct functioning of the IPs and their integration.
Dynamic reconfiguration system allows us to dynamically allocate hardware resources as needed by particular applications. This paper focuses on the application of FPGA-based partial dynamic reconfiguration system (PDRS) with configurable boundary-scan circuit (CBSC), which can be used in many different fields, especially in the military and aerospace fields. Generally speaking, if an important function...
With the wireless communications technology in data security development, it increases the requirements for security and confidentiality, using the security management strategy and security technology faces new challenges. The use of encryption software for wireless communication has become the bottleneck of secure communication system. It is difficult to implement that Commercial MCU to complete...
Article presents modification for the cryptographic hardware accelerators. Modification, which allows for add new functionality to cryptography systems. Functionality allows for the dynamic changes in the number of rounds with maintaining uniformity in the processes of encryption and decryption. The proposed modification was discussed on DES algorithm example.
An FPGA implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves high-speed with little hardware resources using feedback logic and inner pipeline with negative edge-triggered registers. In this way, the delay of the critical path is reduced, without increasing the latency of cipher execution. The proposed implementation reaches a data throughput...
With the combination of PUFs, obfuscation, and multi-boot, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Our particular PUF implementation does not steal valuable FPGA real estate from the actual design with the help of multi-boot. We favor...
A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 128-bit plaintext and the 128-bit initial key, as well as the 128-bit...
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