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Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs -- the Xilinx Virtex-6...
The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture...
Power leakage through side-channels has been utilized by attackers to recover secret information in embedded cryptographic systems, and various countermeasures have been devised to mitigate this kind of leakage. In hardware systems, examples of such countermeasures include power balance circuits and masked gates. Power balance technologies such as Wave Dynamic Differential Logic (WDDL) aim to balance...
Side-channel attacks have been a serious threat to the security of embedded cryptographic systems, and various countermeasures have been devised to mitigate the leakages. Power balance technologies such as wave dynamic differential logic (WDDL) aim to balance the power by introducing differential logic. However, different routing length leads to different capacitance of wire, and this hampers the...
An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation,...
Confidential Information transactions need cryptographic algorithms to give access to data only for authenticated individuals. In the era of smart phones and internet of things, most of the data exchange occurs between small and smart electronic gadgets. Cryptographic algorithms are necessary in smart gadgets to secure the sensitive data. Hardware implementations of cryptographic protocols on ASIC/FPGA...
Using passwords for user authentication is still the most common method for many internet services and attacks on the password databases pose a severe threat. To reduce this risk, servers store password hashes, which were generated using special password-hashing functions, to slow down guessing attacks. The most frequently used functions of this type are PBKDF2, bcrypt and scrypt. In this paper, we...
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources...
This paper describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, which is designed to support both today's and tomorrow's symmetric-key cryptography algorithms and standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only...
Recent research has demonstrated that there is no sharp distinction between passive attacks based on side-channel leakage and active attacks based on fault injection. Fault behavior can be processed as side-channel information, offering all the benefits of Differential Power Analysis including noise averaging and hypothesis testing by correlation. This paper introduces Differential Fault Intensity...
Modern cloud storage requires a high throughput and low latency data protection system, which is usually implemented with an Advanced Encryption Standard (AES) hardware accelerator connected with CPU through PCI Express (PCIe). However, most existing systems cannot simultaneously achieve high throughput and low latency, as they impose conflicting requirements to the block size of packets used in PCIe...
An RTL countermeasure intended to protect the AddRoundKey and SubByte steps of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on first order CPA attacks confirmed the effectiveness of the proposed countermeasure, especially in protecting the SBOX output, showing that even with the acquisition...
A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order...
Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the "leakage" of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA)...
Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even...
In the online world, service providers allow users to upload data to be stored or processed. In some cases, privacy will become an essential feature. Sensitive content can be the data provided to or the services used at the service provider. Logging of the actions of the service providers can therefore also generate privacy-sensitive content. However, to enhance transparency towards users, logging...
This paper shows a multi-purpose System-on-Chip (SoC) platform for rapid prototyping of computation and data intensive applications. The platform is composed of an Intellectual property (IP) modules resource library, a 2D mesh Network-on-Chip (NoC) as communication infrastructure which scales to an arbitrary number of resources, avoiding bus-based communication. A general scheme to plug any IP resource...
The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on some assumed fault model. Our work narrows the gap between both topics. We thoroughly analyse how clock glitches affect a commercial low-cost processor by performing a large number of experiments on five devices. We observe that the effects...
Modern reconfigurable technologies can have a number of inherent advantages for cryptanalytic applications. Aimed at the cryptanalysis of the SHA-1 hash function, this work explores this potential showing new approaches inherently based on hardware reconfigurability, enabling algorithm and architecture exploration, input-dependent system specialization, and low-level optimizations based on static/dynamic...
This paper provides the design of stream ciphers based on hash functions and an alternating step generator based on clock control. The keystream generators used for the design of stream ciphers uses low hardware and low power based circuits called Linear Feedback Shift Register circuits. The first two stream ciphers use toeplitz hash, CRC hash and keystream generation circuits whereas the third one...
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