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An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation,...
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources...
Modern reconfigurable technologies can have a number of inherent advantages for cryptanalytic applications. Aimed at the cryptanalysis of the SHA-1 hash function, this work explores this potential showing new approaches inherently based on hardware reconfigurability, enabling algorithm and architecture exploration, input-dependent system specialization, and low-level optimizations based on static/dynamic...
AES-GCM(Advanced Encryption Standard with Galois Counter Mode) is an encryption authentication algorithm, which includes two main components: an AES engine and Ghash module. Because of the computation feedback in Ghash operation, the Ghash module limits the performance of the whole AES-GCM system. In this study, an efficient architecture of Ghash is presented. The architecture uses an optimized bit-parallel...
This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless...
This paper presents the results of the dependability validation of a cryptoprocessor to SEU effects. The dependability validation was carried out running a testbench, initially using functional simulation, and later using in-system hardware execution. For the fault injection, a modified memory cell and a strategy of pseudorandom generation of states into FSMs are proposed. The testbench was simulated...
In cryptography and information security, hash functions are considered as the "Swiss army knife" - they are used in countless protocols and algorithms. In 2005, we witnessed a significant theoretical breakthrough in breaking the current cryptographic standard SHA-1. Although there is another family of standardized hash functions called SHA-2, ready to replace SHA-1 hash function, at the...
This paper present a design of RSA-encryption using Pipelined radix-2 Montgomery's architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the...
Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. Hash functions are important security primitives used for authentication and data integrity. The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used...
GMAC (Galois Message Authentication Code) is a special case of authenticated encryption mode GCM (Galois/Counter Mode) when it acts as a stand-alone MAC. As the hash function of GMAC, Ghash is based on the GF(2128) multiplier. It is the algebraic properties of Ghash that support incremental authentication of GMAC. In this paper, an efficient hardware implementation on Xilinx Virtex 5 FPGA platform,...
Secure Hashing Algorithm (SHA) is increasingly becoming popular for the online security applications, specifically, for mobile and embedded system platforms. This necessitates a high performance hardware implementation of the four most utilized SHA algorithms (SHA-224, SHA-256, SHA-384, SHA-512). This paper presents a reconfigurable SHA-2 IP core utilizing the available hardware for computing SHA-384/...
The FPGA performance of ciphers mainly includes area and throughput of implementation. In this design, several cryptographic algorithms such as SMS4, AES and Camellia have been implemented to analyze their performance and study the influence of the area with two different LUT-size FPGA devices. This paper uses VHDL to describe circuit function, choose Altera Stratix II and Cyclone II devices to simulation...
In the block ciphers, though the operation is quite complex, there are a lot of similar characteristics including arithmetic unit, operation width, parallel data and ordinal implement. It is very suitable for designing ASIP (application specific instruction set processor) targeted at block ciphers. In this thesis, a reconfigurable processor architecture is proposed, At the mean time, in order to improve...
SMS4 is a 32-round block cipher with a 128-bit block size and a 128-bit user key. This paper presents rolling and unrolling field programmable gate array implementation of the SMS4 algorithm, and both the encryption and the decryption algorithms of SMS4 have been implemented on the same FPGA. The rolling design of SMS4 for area requires 1552 ALMs, the maximum operating clock is 139MHz and the corresponding...
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