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In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean...
A 1 Volt, 8-bit, Successive Approximation Register Type ADC, with variable conversion time is implemented using FPGA SPARTAN-6 Board. The proposed ADC is design to achieve different number of conversion cycle for different sample values. Input signal as triangular wave with both positive and negative cycle is taken, But the DAC used in feedback is design to give analog output only for positive cycle...
Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly...
In this paper, we propose a novel high-speed and SPA-resistant architecture for elliptic curve cryptography (ECC) point multiplication. A new Karatsuba-Ofman based pipelined multiplier is proposed to lower the latency, and an improved comb point multiplication method is employed to reduce the clock cycles and to resist simple power analysis (SPA). The proposed ECC architecture has been implemented...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
In this paper, three different approaches are considered for FPGA based implementations of the SHA-3 hash functions. While the performance of proposed unfolded and pipelined structures just match the state of the art, the dependencies of the structures which are folded slice-wise allow to further improve the efficiency of the existing state of the art. By solving the intra-round dependencies caused...
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
This paper describes an on-going work aiming at using FPGAs as a fast prototyping environment for Token-based Self-timed processors, inspired by the Octasic asynchronous design technique. Originally developed for Digital Signal Processing, this design technique is adapted here for an FPGA-based general purpose processor. The paper emphasizes improvements to existing FPGA implementation methodologies...
We present a digital implementation of a correlation receiver for pulsed CDMA lidar signals in direct-time-of-flight systems. A coded time-of-flight lidar is capable to identify its own signals and to reject state-of-the-art uncoded or differently coded pulses. The required sampling rate of the system ADC is determined. For processing the digitized receive signal a correlation filter realized in FPGA...
Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced:...
A new approach to introducing computer architecture in introductory logic design courses based on Babbage's difference engine is described. The difference engine is the thread that students follow from logic design to the concepts associated with a basic load/store microprocessor architecture.
We present TLegUp, an extension of LegUp, that automatically generates Triple Modular Redundant designs for FPGAs from C programs. TLegUp is expected to improve the productivity of application designers for space, to allow designers to experiment with alternative application partitioning, voter insertion and fault-tolerant aware scheduling and binding algorithms, and to support the automatic insertion...
Fault injection is a well-known technique to evaluate the susceptibility of integrated circuits to the effects of radiation. In this work, an existing emulation-based methodology is extended, updated and improved under the name of NETFI-2. Preliminary results show that NETFI-2 provides accurate measurements while improving the execution time of the experiment by more than 300% compared with other...
Chaotic systems can be used for secure communication such as transmitting video, audio and text files. Various chaotic generators have been implemented on FPGA in realtime for synchronous communication applications. In this paper, a detailed design approach is presented to implement modelbased chaotic generator designs on FPGA. Henon map has its significance in studying chaotic systems and is used...
The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and reaches a rate of up to 103.82 million samples...
This paper explores the capabilities and limitations of soft GPGPU-based computing on fixed-point arithmetic. The work is based on an existing soft GPU architecture which has been improved and extended to cover broader benchmarks. A generic ALU design for modern FPGA architectures is presented. The enhanced ISA includes conditional instructions and global atomic operations. We extended the tool flow...
FPGAs have evolved rapidly over the past decade with a significant increase in size and complexity. Today's FPGA is indeed a system-on-chip (SOC) with a wide variety of hardened functionality, multiple asynchronous clock domains and widening interactions among different parts of the chip. It is commonplace to find applications that transfer data and control across clock-domains. This growing complexity,...
In this paper, we propose the design of globally asynchronous locally synchronous (GALS) pipelined 16-bit Baugh Wooley multiplier for digital signal processing applications. The primary emphasis of the design is on low power implementation of multiplier. For fair bench marking fully synchronous pipelined 16-bit Baugh Wooley multiplier and GALS pipelined 16-bit Baugh Wooley multiplier are implemented...
Semiconductor industry has been putting tremendous efforts on 2.5D technology in accordance with the increasing demand for better capacity and system performance. This technology enables several dies to communicate up to the speed of Gigabits per second while reducing the cost for a system with heterogeneous components. However, such new technology also poses great challenges whereby the manufacturing...
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