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Optical interconnection is a potential substitute for electrical interconnection in the chip integration field, as it can ultimately solve the problems such as crosstalk and electric migration brought by electrical wires. In the paper, a short frame asynchronous optical communication protocol is proposed to implement the inter-chip optical communication between the microprocessor and the static memory...
The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
This paper proposes a novel high-speed vision processor based on pixel-parallel PE array. The processor consists of a pixel-parallel PE array, an embedded RISC core, an AHB bus, some SRAM blocks and other logical controllers. PE array performs the low- and mid-level vision processing, and RISC core carries out the high-level vision processing in succession. The vision processor can process vision...
This paper presents the design of a many-core computer architecture with fault detection and recovery using partial reconfiguration of an FPGA. The FPGA fabric is partitioned into tiles which contain homogenous soft processors. At any given time, three processors are configured in triple modulo redundancy to detect faults. Spare processors are brought online to replace faulted tiles in real time....
As the chips get denser and faster, heat dissipation is fast turning into a major problem in development of ICs. Nonuniform heating of chips due to hotspots is also an area of concern and much research. In this paper, we propose an adaptive method which takes advantage of the self-reconfiguration capability of modern FPGAs to mitigate hotspots. We adapt the floor plan of the IC in response to the...
The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial reconfiguration to remove SEUs from the configuration memory of the FPGA. Although the FPGA is subject to...
The possibility to adapt in-flight the behaviour of a space-based equipment to different operating conditions and/or new functional requirements is of paramount importance in the field of the commercial multimedia communications. In fact, in a satellite lifetime of 15 years, new standards may arise, the existing one may be upgraded, or the opportunity to introduce new added-value services may be considered...
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also...
For the secure transaction of data between the central processing unit (CPU) of a satellite on board-computer and its local random access memory (RAM), the program memory has been usually designed with triple modular redundancy (TMR), which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. TMR error correction technique allows...
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and practical solutions to improve the security of FPGAs. In this paper, we investigate a method to perform a secure dynamic partial reconfiguration of SRAM FPGAs using embedded processor cores. Two schemes based on hard-wired...
The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based...
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