The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a scalable MIM capacitor model that is applicable at RF and mm-wave frequencies. The model parameters are obtained from electromagnetic simulations and verified by measurements over a wide range of geometry parameters. A de-embedding method is described that is based on two through structures.
This paper presents a power-loss model for Lateral- Diffused MOSFETs (LDMOSs) in application-specific integrated circuits (ASICs) in the field of wireless power-transfer system applications. Both the transmitter and receiver power-stages integrated in their respective ASIC units were considered, and the total system efficiency was subsequently estimated. Layout parasitics pertaining to the primary...
Electromagnetic Interference (EMI) becomes one of emerging issues for recent designs because LSI-Package-Board system is getting larger and more complicated. There are difficulties in simulating and understanding causes of EMI-noise. However there are few papers discussing simulation methods and root cause analyses for EMI-noise issues. This paper proposes a new efficient and quick method based on...
Co-Design with Optimization of Physical Plane Layout in FCBGA substrate is imperative for the high-speed chips to perform the best performance. It was found that ground metal plane void (anti-pad) under ball pads and core via pads had correlation with insertion and return loss. We focused on optimizing metal and trace layout of the high-speed signal net, also known as SerDes (Serializer-Deserializer)...
Users of test equipment such as oscilloscopes expect performance and accuracy beyond the level of their device under test in order to insure measurement results correspond to the DUT, not to limitations of the test equipment. This drives the use of bipolar circuitry at the front-end of high-bandwidth oscilloscopes, even if targeted at testing devices in a marketplace dominated by CMOS. Several circuit...
This paper proposed a novel layout for cross-coupled pair to reduce its extrinsic resistive and capacitive parasitic parameters and another layout for differential pair to decrease the influence of Miller effect and some other parasitic effects. The equivalent circuits of the extrinsic parasitic network of these two structures are first derived and validated using EM simulation. The extraction equations...
In this paper a fast parasitic-aware synthesis approach of CMOS analog circuit is presented. Instead of the conventional approach of circuit sizing followed by layout generation, extraction and verification, we propose a method that considers the performance constraints and layout induced parasitics simultaneously within a concurrent phase of circuit synthesis. The proposed methodology is tested with...
The mathematical modeling and analysis of various CPW discontinuities are presented in this paper. Simulations of these discontinuities are done through ADS and its electrical equivalent parameters are evaluated through MATLAB programming (M-file) for open, short and GAP. And compared with closed form relations. Various discontinuities analyzed are open end, short, step, GAP, bend. The analysis is...
In this paper we discuss the efficiency and accuracy of extracting potential bridging fault sites from a physical layout specification. Using a combination of developed tools and common layout and extraction tools, a fault file is generated with an ordered list of the most likely to occur bridging faults based on parasitic capacitance values. These faultsare then simulated and results are discussed...
This paper presents a novel automated post-layout flow validation tool to intensively test the MOSFETs and passive components in 32nm, 28nm and 22nm Process Design Kits (PDK). Benchmark circuits, such as, ring oscillator, logic circuits and passive delay circuits, are automatically generated, LVS (layout versus schematic) checked, extracted and simulated in multiple Model/LVS/Parasitic extraction(PEX)...
In this work we study improvements of the high-frequency noise performance of HBT devices by means of layout and spacer optimization. Using an equivalent circuit, we identify the dominant noise sources and demonstrate that the reduction of the base-resistance induced thermal noise by means of dotted emitters in combination with lowering the edge contribution of the base-emitter capacitance (e.g. by...
This paper presents the quasi-adiabatic Asymmetrical Positive Feedback Adiabatic Logic (APFAL) for low power operation through energy recovery technique. The topology of a logic gate defines the logic effort and it determines the gate sensitivity. The APFAL strives to reduce the logic effort of one arm of the 2N2P latch which results in reduced values of adiabatic and non-adiabatic power components...
This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit...
We present a nano-scale early-design-stage prediction methodology for crosstalk-induced power using our new interconnect density function, the IDF. Unlike previous methods that use layout information, in our method a high-level circuit description is enough to accurately predict the crosstalk-induced power and no layout information is needed. The credibility of our prediction has been verified using...
Performance of analog integrated circuits is highly sensitive to layout parasitics. This paper presents an improved template-based algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to achieve desired circuit performance, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm...
This paper is discusses about parasitic effect of spiral inductors on 5.8 GHz low noise amplifier (LNA) performances based on 0.5 mum GaAs pHEMT technology. Using S-parameter simulation, performance of the LNA between lump and distributed circuit are compared at 5.8 GHz. Electrical performance of the LNA performances by placing ideal components with non-ideal components shows that noise figure is...
This paper presents an interface circuit for CMOS-MEMS gyroscope using integrated diode-rings. A brief introduction for the CMOS-MEMS integration technology [1] using high-ratio isolation trench will be introduced first. The integration system contains a Z-axis capacitive bulk silicon gyroscope and an interface circuits using diode-ring doing the first demodulation. A detailed analysis for the integrated...
We present a flow to extract, simulate and generate test patterns for interconnect open defects. In contrast to previous work, the accuracy of defect modeling is improved by taking the thresholds of logic gates as well as noise margins into account. Efficient fault simulation is enabled by employing an aggressive fault collapsing strategy and an optimized fault list ordering heuristic which allows...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.