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We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
This paper describes the technology-independent approach for FPGA (Field-programmable gate array) and ASIC (Application Specific Integrated Circuit) implementations. This approach is based on the reuse of portable building blocks described at RTL level, thus the design can be mapped to an ASIC or an FPGA devices with few RTL code changes when migrating between FPGA and ASIC. As case study, an OpenRISC...
This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions:...
Multiply and Accumulate is the main component of the DSP System, which is the major block for power consumption and decides the speed of the overall system due to its complex operation. Hence in most of the DSPs, it lies in the critical path. In this work, Low power MAC architecture has been proposed by examining the critical paths and the hardware complexities. Proposed is a generic architecture...
To achieve high computational efficiency by maintaining low power and area requirement is becoming vitally important task for many computationally intensive applications in mobile devices. Designing an architecture for such complex application on ASIC is the traditional method which gives good performance by sacrificing flexibility. The many researchers are trying to achieve both performance and flexibility...
Floating-point square root is a fundamental operation in signal processing and various HPC applications. Since this is an expensive operation in resource and energy consumption, its efficient implementation should be of priority in future multicores that will face dark silicon issues. This paper presents a low-cost, low-power consumption design to calculate the square root using the IEEE754 single-precision...
The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. The interleaving, one of the key components in the communication baseband, varies in differing communication protocols. A novel reconfigurable variable increment step (VIS)...
The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written...
The LSI design methodology against Differential Power Analysis (DPA) is important to realize a tamper-resistant cryptographic circuit. In order to verify the DPA resistance before ASIC fabrication, the DPA verification using FPGA is commonly used. However, power traces of ASIC differ from that of FPGA, so the DPA verification on FPGA cannot guarantee the DPA resistance on ASIC. On the other hand,...
Correlation power analysis is the well-known attack against cryptographic modules. An attacker exploits the correlation between the power consumed by a device and the data being processed. In the present paper, we present the experimental procedure of correlation power analysis using three different devices: FPGA, ASIC and a microcontroller. Results show that the power model used to calculate hypothetical...
Electronics cryptographic devices can be attacked by monitoring physical characteristics released from their circuits, such as power consumption and electromagnetic emanation. These techniques are known as Side Channel Attacks (SCAs). The Differential Power Analysis (DPA) is one of the most effective SCAs, which can reveal the secret key from the dependency between power consumption of the device...
This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time. Real-time processing allows duty cycling of the analog frontend, which is key to achieve low power consumption. The architecture consists of a programmable application specific instruction set processor and a set of application specific integrated circuits. The design...
Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level...
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA-based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main...
Executing various combinations of external locating techniques provides many benefits over tracking and locating systems based on radar or GPS. These embedded radio positioning applications are built on a common set of functional capabilities. Development of a specific positioning system involves selection of a subset of these capabilities and implementation into a physical form that meets the size,...
Differential power analysis experiments are conducted on various ASIC implementations of AES with different S-box architectures: (i) an inverter over Galois field GF(((22)2)2), (ii) table, (iii) PPRM (positive polarity Reed-Muller forms), and (iv) 3-stage PPRM. Dedicated ASIC is developed and its power is measured on the standard evaluation board SASEBO-R. The results show that the S-box implementations...
The ultimate research goal for unmanned aerial vehicles (UAVs) is to facilitate autonomy of operation. Research in the last decade has highlighted the potential of vision sensing in this regard. Although vital for accomplishment of missions assigned to any type of unmanned aerial vehicles, vision sensing is more critical for small aerial vehicles due to lack of high precision inertial sensors. In...
We introduce two approaches for power saving routers, which are the power efficient designing and the power saving designing. Power efficient designing enables a high performance router at low power consumption. As a part of power efficient designing, we have integrated ASICs/FPGAs of routers and developed a scalable central architecture. Additionally, we used new high speed memories and high speed...
Energy harvesting systems are becoming more attractive for remote sensing applications. In this paper, we propose a new technique that performs the voltage scaling in conjunction with frequency scaling to achieve ultra low power design in ASIC/FPGA. To detect errors and obtain the corrected data without any loss in performance, a delayed clock flip-flop is utilized to borrow timing from non-critical...
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA architectures. The dynamic power consumption of the fine-grained units is obtained using standard FPGA tools, and the coarse-grained units using standard ASIC tools. Based on this approach, the dynamic power consumption...
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