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In this paper we introduce a jigsaw-puzzle model to instill an entrepreneurial mindset in students. We then use our model to craft and add innovative lab assignments to “Digital Systems”, which is a core course taken by Electrical Engineering, Computer Engineering and Computer Science students worldwide. In each lab assignment, students are provided with some components or puzzle pieces as well as...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
A proposed high speed generic floating point algorithm for 12-Bit Architecture is consist of adder, subtractor, multiplier, divisor, square root, and cube root modules. A novel algorithm was proposed for each modules using VHDL to optimize the speed and area as well as to attain the highest maximum operating frequency. A top down approach was applied for the modules and these were further subdivided...
Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced...
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC)...
FPGA based Fault injection and Fault tolerance techniques are used to evaluate and validate the reliability of VLSI circuits. This approach combines the efficiency of hardware based techniques and the flexibility of simulation based techniques. The system efficiency and robustness increases as the reconfiguration of FPGA is not needed for each fault experiment. Fault injection is performed using commercial...
Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process,...
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application designers tend to rely on less efficient off-the-shelf operators. To address this issue, an open-source architecture generator framework is introduced. Its salient features are an easy...
This paper presents the implementation and delivery of a microprocessor based design laboratory, in an attempt to achieve tighter integration with theory and improve student's performance. The design process follows a hierarchical structure, requiring students to first build basic devices such as logic gates, multiplexers, one-bit memory cells etc. These basic devices are then used to build an ALU,...
A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
A new high precision serial multiplier with most significant digit first (MSDF) is presented. This one uses a borrow-save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
Fully-pipelined simple modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N = 4. It is shown further that the HT of transform-length N = 8 can be obtained from two 4-point HT modules, and similarly, the HT of transform-length...
It is known that fast, fully combinational leading-digit detector circuits can be generated efficiently by recognizing their inherent hierarchical structure. It is shown herein that this structure is not only hierarchical, but also recursive. This recursivity fully defines a minimal-complexity circuit, thus guaranteeing optimal circuit synthesis. Such a circuit having an N-bit operand generates all...
This study presents a high-performance position controller for permanent magnet linear synchronous motor (PMLSM) drives based on FPGA (field programmable gate array) technology. Firstly, a mathematic modeled for PMLSM drive is defined. Secondly, to increase the performance of the PMLSM drive system, an AFC (adaptive fuzzy controller) constructed by a fuzzy basis function and a parameter adjustable...
This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients. The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop. All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM. The program...
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