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This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing...
Among many parameters that are crucial for performance of FPGA (Field Programmable Gate Arrays) structures the high operation speed combined with reasonable and cost-efficient layout seems to be the most important feature. In pace with evolution of FPGA structures a common belief has spread out that each subsequent FPGA structure, originated from the same family, is better than its predecessor in...
The software BOOLE-DEUSTO is oriented to the design of digital electronic circuits from the student point of view. On the other hand, WebLab-DEUSTO is a well known remote laboratory, and one of the implemented experiments is focused on CPLD and digital electronics. The objective of this paper is to describe the results of connecting BOOLE-DEUSTO and WebLab-DEUSTO. Under this common approach, a novel...
The paper describes the use of an FPGA Spartan-3E board in a Digital Logic Design course to synthesize music for students who have no or minimal background in Electrical and Computer Engineering. The authors hope that this paper may be used as a reference to build a better Digital Logic Design course.
The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FPGAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However,...
We show NBTI delay degradation considering variations in a 65 nm process. We evaluate these two models. The homogeneous degradation model (HDM) assumes that NBTI degradation is constant at any variation and the inhomogeneous degradation model (IDM) assume that it is larger at the fast condition. In the usual logic gates on ASICs, delay degradation becomes much smaller on IDM. Circuit design guardbands...
The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of timing unbalance. First, we propose...
Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes...
Radiation effects on SRAM-based FPGA configuration memory induce unique failure modes that cannot be found in similar ASIC devices and can translate into permanent errors in the circuit mapped into the FPGA. The physical layout of the mapped circuit has a considerable impact on the overall reliability of the implemented circuit. In this work we present a set of soft error reliability aware placement...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
This paper describes a design of a training system for a combinational logic design course. The goals of this design are to reduce a cost of the system and to lower the lost and damage of TTL elements used in a digital laboratory currently. The system uses a Field Programmable Gate Array (FPGA) as a processor containing basic logic gates, and uses a microcontroller as a gate selector. The training...
This survey first introduces index generation functions, which are useful for pattern matching in the communication circuit. Then, it shows various methods to realize index generation functions by using LUTs and memories. These methods are useful to design FPGAs with embedded memories.
Due to direct impact on power supply and thermal component selection, power consideration within the system power budget and operation environment is becoming increasingly important. In this paper, it analyses the sources of FPGA power consumption, present situation, design consideration, popular technologies and analysis tools, etc. It will give readers a general understanding of power consumption...
Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical...
In this paper we present a new software framework to analyze and modify circuits netlists in an automatic fashion. We developed an API that implements low-level functionalities above which it is possible to create complex algorithms. We then developed a second software layer to implement hardening techniques for Single Event Effects (SEEs) in digital microcircuits. Experimental results prove the effectiveness...
In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we...
Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event...
This paper proposes the design of PI-like fuzzy logic controller (PIFLC), on Field Programmable Gate Array (FPGA) device which improve speed, accuracy, power, compactness, and cost effectiveness. The design utilizes 1260 slices of the target FPGA, and is able to produce an output at 6μs. The proposed controller is tested with a first order system. The experimental results were compared to the simulation...
The Wave Dynamic Differential Logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design....
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this...
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