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This paper presents an approach to reduce the power consumption of FPGA based digital circuits at FSM design level. The approach is based on clock gating technique. By using control signals at FSM level, we have limited the clock switching and other signals transitions in the system, leading to reduced dynamic power consumption of the systems. Our results have shown up to 7% reduction in dynamic power...
We present an extensible automation framework for constructing and optimizing large-scale regular expression matching (REM) circuits on FPGA. Paralleling the technique used by software compilers, we divide our framework into two parts: a frontend that parses each PCRE-formatted regular expression (regex) into a modular non-deterministic finite automaton (RE-NFA), followed by a backend that generates...
In this paper, a WiMedia UWB MAC layer is implemented in a FPGA development board. The MAC layer protocol is modeled by FSM technique and written in hardware description language. Combining the MAC layer design with other standard system peripherals, a FPGA-based UWB MAC reference design supporting UWB PHY layer specifications is synthesized. To verify the design, the FPGA platform works with a pair...
Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced...
The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically...
This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs...
A general purpose CCD controller that can address any CCD, has been developed at the Indian Institute of Astrophysics. It is based on a Digital Signal Processor (DSP) chip, Motorola DSP 56002 for implementing essential operations such as read-out of the CCD, interfacing with the host and correlated double sampling for reset noise elimination. In order to reduce the chip count and size of the controller...
The method of synthesis and implementation of Mealy finite state machines into FPGAs is proposed in this article. Synthesis method is based on the architectural decomposition of logic circuit of automaton and multiple encoding of microinstruction executed by implemented control algorithm. All microinstructions are divided into subsets based on a current state. Then, they are encoded separately in...
The method of synthesis and implementation of Mealy FSMs into FPGAs is proposed. Synthesis is based on the architectural decomposition and multiple encoding of internal states. States are divided into subsets based on a current state and encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state. It leads to implementation...
Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. In this paper the hardware implementation of optimized area for the block cipher advanced encryption standard (AES-128) is introduced using field programmable gate array (FPGA). The core includes the key schedule expansion and storage, the encryption, the decryption, and...
Reuse-based intellectual property (IP) design is one of the most promising techniques to take the SoC design quickly into market. To facilitate better IP reuse, it is desirable to have IP exchanged in the software form such as hardware description language (HDL) source codes. However, soft IP has higher protection requirements than hard IP, and most existing hard IP protection techniques are not applicable...
A typical student project in a digital system design or a computer organization course is the design of a CPU for a small, simplified instruction set. However, it can be a challenge to devise such projects in a way that simultaneously reinforces effective logic design principles, is hands-on, can be completed using inexpensive and standard laboratory equipment, and (most importantly) inspires, as...
Controllers implemented as finite-state machines (FSMs) occupy a major portion of FPGA designs. These FSMs can be implemented on synchronous embedded memory blocks (SEMBs) in current FPGAs. This approach, in addition to reducing considerable amount of power, also has several implementation benefits. In this research, we propose to further minimize the power consumed by the FSMs that are mapped to...
Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation...
The implementation of inverse kinematics and servo controller for robot manipulator using FPGA (field programmer gate array) is investigated in this paper. Firstly, the mathematical model and the servo controller of robot manipulator are described. Secondly, the inverse kinematics is formulated. Thirdly, the circuit design to implement the function of inverse kinematics and servo controller based...
Domain-specific design flows can enable an efficient path to implementation, as well as making the design process intuitive and the designs reusable. When targeting FPGAs, there are few techniques in high level synthesis that enable thorough exploration of the inherent flexibility of the FPGA fabric as an implementation medium. In this paper, we propose a new methodology, based on micro-coded datapaths,...
The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions have become a necessary and basic capability of intrusion detection systems, but their implementation tends to be expensive in terms of memory cost and time performance. This work provides an architecture that reduces the...
The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal...
The basic structure and features of a 16-bit real time stack processor is introduced. The design and implementation method of the 16-bit stack processor is presented in the paper. The behavioral description and state machine description is applied to program design using VHDL. The 16-bit real time stack processor implemented by Spartan-II XC2S200 FPGA chip, and is successfully adopted in frequency...
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