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The following topics are dealt with: analog circuit techniques; digital signal and data processing; VLSI design; RF technology; system on chip; testing and formal verification; digital circuits; MEMS devices and applications; clocks and data recovery; CAD for VLSI; device characterization and modelling.
A new analytical synthesis method for high order multiple output current-mode general filter structure is described. This method is based on the decomposition of the n-th order general transfer function into n-first order equations plus one equation for the realization of the n-th output current. Based on this method, a proposed n-th order current-mode simultaneous output filter structure is presented...
It is presented an implementation, at the transistor level, of a field programmable analog array using the switched current technique (SI). Programmable macro-cell blocks are designed using the class AB grounded gate memory cell which performances have been already improved regarding to SNR and bandwidth. The configurable blocks can be sampled up to 40 MHz. The proposed programmable block necessitates...
This paper presents a CMOS fully differential current feedback operational amplifier with controllable 3-dB bandwidth. The FDCFOA has the advantage of a wide range controllable 3-dB bandwidth (~57 MHz to 500 MHz) without changing the feedback resistance. The FDCFOA has a standby current of 320 mu A. PSpice simulations of the FDCFOA block were given using 0.25 mum CMOS technology from AMI MOSIS and...
In this paper, we investigate a 5.25-GHz highly integrated CMOS class-AB power amplifier for IEEE 802.11a WLAN. The proposed power amplifier is implemented with a two gain-stage structure which is followed by an off-chip output matching circuit. Moreover, a transistor-level compensation technique is employed to improve the linearity. The measured results indicate an over 20% power-added efficiency,...
A new balanced input balanced output switched capacitor (SC) bandpass lowpass filter using the current feedback operational amplifier (CFOA) is presented. The proposed SC biquad filter is based on a new balanced input balanced output lossless and lossy integrators. The introduced filter has the advantage of independent control Q,omegao and the balanced operation. PSpice simulation results for the...
A novel low noise CMOS regulated cascode (RGC) transimpedance amplifier, which can be used in the front-end of 2.5 Gbit/s optical communication system, is presented. Active inductor peaking technique, active feedback and source follower are used to improve the -3 dB bandwidth. Simulation results using 0.18 mum standard CMOS process show the transimpedance gain is 71.51 dBOmega, the -3 dB bandwidth...
A major component of a mobile robot system is the ability to navigate accurately in unknown environments with little or no human intervention. In this paper, we present a modular and cost-effective navigation technique incorporating signals from RFID tags, an RFID reader, and a fuzzy logic controller (FLC). The RFID tags are placed at 3-dimensional positions in the robot's workspace in such a way...
Traditionally, G.729 Annexure A and B and other speech codecs are implemented on programmable digital signal processors (DSPs). This paper presents the implementation of G.729 A/B on field programmable gate arrays (FPGAs). This implementation has improved performance in terms of computational delay and memory as compared to its implementation on DSPs. The advantage of reduction in the computational...
Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. In this paper the hardware implementation of optimized area for the block cipher advanced encryption standard (AES-128) is introduced using field programmable gate array (FPGA). The core includes the key schedule expansion and storage, the encryption, the decryption, and...
The advanced encryption standard (AES) is a symmetric key block cipher that has been approved by NIST as a replacement for the data encryption standard (DES). In this paper, we present an FPGA implementation for AES. Unlike most of the common implementations that support only ECB mode, our design supports five modes of operation. In particular, it supports ECB, CBC, CFB, OFB and CTR modes. The design...
In this paper, the modified mid-band exchange coefficient (MMBEC) image watermark technique has been realized on FPGA platform. This technique is implemented on Xilinx XCV800-pq240 chip and Labview software as graphical user interface. The MMBEC technique utilizes 49% of the chip area and operating maximum frequency of 36 MHz. A performance comparison between the software and hardware implementations...
In this work, ITU-T G.729 speech codec is precisely modeled using basic building blocks of SIMULINK such as simple adders and multipliers. Therefore, a golden model of the codec which best suits as a reference for its hardware implementation is developed. In a custom hardware design, the precision of the computations, i.e. the optimum number of the bits of the computational blocks should be calculated...
The paper presents a preliminary approach for the modeling and simulation of a complete wireless sensor network with two nodes using SystemC-AMS, an open-source C++ library dedicated to the description of heterogeneous systems containing digital, analog, RF hardware parts as well as embedded software. The WSN node, or mote, detailed herein consists of a physical sensor, a continuous time sigma-delta...
A new technique to implement digital interpolation filter is presented in this paper. The technique employs a sample calculation functional block which reduces the hardware required to realize the filter by orders of magnitude. The filter is realized with 80times160 mum2 using 65 nm CMOS technology. Over Sampling Rate of up to 256 is achieved for 16-bit digital data sampled at 705,600 bps. The filter...
We propose a novel, high-speed, low-area architecture for multiplication over GF(2m). The proposed architecture is processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. Our architecture requires only m processing elements as compared to m2/2 for the...
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