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This paper introduces and details a Built-In Self-Test (BIST) approach designed for the embedded Block Random Access Memories (BRAMs) found within Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). The BIST is designed to test the BRAMs in all configurable modes of operation including single-port, dual-port, first-in first-out (FIFO), first-in first-out with error correcting code (FIFOECC), and...
This paper introduces a process to select different test circuit using FPGA controlled pull and disconnection of relay matrix, so that multi-port equipment testing could be achieved. This design, to some extent, has a simplified circuit complexity and an increased, comparing to the test equipment previously used.
Ball grid array (BGA) packages have gained wide acceptance for use with FPGAs and the devices are used extensively for digital electronic designs. While these packages provide high interconnect densities, they rely upon an array of closely-spaced solder balls that are subject to cracking, oxidation and eventual failure. These solder joints can contribute to costly intermittencies that drive ldquono...
Fault-tolerant architectures based on physical replication of components are vulnerable to faults that cause the same effect in all replica. Short outages in a power supply shared by all replica are a prominent example for such common cause faults. For systems in which the provision of a replicated power supply would cause prohibitive efforts the identification of reliable countermeasures against...
A hardware design of a configurable and extensible processor named Tcore, which is based on transport triggered architecture (TTA), is presented in this paper. Due to its flexibility, the Tcore can be used as an application specific processor, especially as a coprocessor for different DSP applications. We have configured Tcore to an instruction level parallel processor to support the application of...
A minimum development system based SOPC is designed as well as the design thought of the system and its realization way are explained. With a PFGA as the core, this system has compact structure and embodies the characteristics of SOPC system such as high integration and strong flexibility. The cheaper chip with excellent interchangeability is selected and used in the design plan to reduce the cost...
This paper presents the implementation of a JPEG encoder that exploits minimal usage of FPGA resources. The encoder compresses an image as a stream of 8times8 blocks with each element of the block applied and processed individually. The zigzag unit typically found in implementations of JPEG encoders is eliminated. The division operation of the quantization step is replaced by a combination of multiplication...
A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test...
A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array (FPGA) devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.
In this paper we investigate several common bus architectures and measure effective bandwidth between High Performance Computing cores and off-chip memory. Contributions of this paper include (i) characterizing the behavior of four common organizations using off-the-shelf IP cores, (ii) an investigation of the effect of multiple computational cores sharing the bus structures, and (iii) the development...
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented...
A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number...
Structured ASICs have emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. Though the structured ASIC fabric attacks mask and other fixed cost it does not solve verification, particularly physical verification issues with ASICs or logic errors missed by simulation which would require re-spins. These can be avoided by testing in-system with an FPGA and migrating...
This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability...
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