The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to find Critical points - the places, where faults are difficult to detect. The partial duplication of the design with regard to these critical points is able to increase the faults coverage with a low area overhead cost. Due to...
The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are "Moore" type. Each state machine is divided into three...
The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed...
We propose a method to efficiently design a "parity generator", which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to...
The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters. Combinatorial circuit benchmarks have been considered in all our experiments...
A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our...
This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability...
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults
The methods how to design a fault-tolerant system based on FPGAs is presented. The evaluation of the whole design according the computations of reliability and dependability characteristics is described. The formal dependability model and computations obtained on the base of this model is summarized.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.