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In this paper, a low power and low noise eight-channel analog front-end (AFE) IC for portable brain-heart monitoring applications is presented. The developed IC features a fully integrated eight-channel design which includes one channel for diffuse optical tomography (DOT), three channels for electrocardiography (ECG), and four channels for electroencephalography (EEG). In order to achieve the targets...
This paper presents a low-power speed-scalable 8bit Successive Approximation Register (SAR) ADC implemented in 0.18-μm CMOS. By designing a compact asynchronous controller and a charge-sharing DAC, the power consumption can be linearly scaled with the conversion speed. A maximum power dissipation of 28.4 μW and 0.019 mm2 total area make this ADC ideal for highly integrated wireless sensor nodes. The...
A pipelined ADC equation-based design space exploration methodology targeting minimum power dissipation is presented. While distinct frontiers are drawn between system-level and circuit-level design phases, this paper shows the importance of a refinement step between both phases. At the system-level, all possible architectures are examined followed by behavioral validation. Using a circuit sizing...
This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype...
Complementary metal oxide semiconductor (CMOS) image sensors are more compatible than charge coupled devices (CCDs) for lab-on-a-chip platforms due to their inherited advantages. However, without the noise reduction circuits, CMOS technology wouldn't be able to compete with CCDs. Today, correlated double sampling circuits (CCDs) are used in all CMOS imagers in order to remove the reset noise and the...
A novel circuit breaker closing resistance instrument is designed in this paper. Super capacitor was used as test power source, and a digit signal processor as microcontroller, moreover AD526 and LM324 were used for signal amplifying and filtering. On-chip Analog-Digital converter was used to acquire voltage data. Closing resistance, loop resistance, and pre-insertion time can be measured in one closure...
A new kind of differential comparator is presented. A differential difference amplifier circuit is used to compare analog input signal and reference voltage. The experimental results show that the comparator improves speed and power performances compared with traditional comparators. The comparator is implemented in SMIC0.18 CMOS process, consumes 0.9 mW, and has a layout size of 508 μm2.
In this paper, a practical analog implementation of capacitor charge balance controller is presented, which is capable of achieving the optimal response for dc-dc Buck converters without relying on the knowledge of the nominal passive component (output inductor and capacitor) value. This ready-for-integration analog controller applies the output voltage curve analysis for deriving the formulas to...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
The performance of data converters has been pushed relentlessly over the years, leveraging advancements in scaling and design techniques that exploit the high density and speed of modern process technology. However, most of the underlying architectures in use today were conceived decades ago, and are nowadays regarded as fundamental in their nature. Were these architectures viewed as fundamental,...
Applications such as sensor networks and medical monitoring often require ADCs that can digitize signals with varying bandwidth and dynamic range requirements. In energy-constrained systems, it is beneficial to adapt the ADC performance to the signal to avoid consuming power on unnecessary bandwidth or accuracy. Therefore, this paper presents a single reconfigurable SAR ADC whose power scales with...
In this paper, a prototype delta-sigma ADC is implemented in a 0.18μm 2P5M CMOS process. The input signal sampling capacitors are shared with the front-end DAC capacitors. The sampling frequency is 50MHz and oversampling ratio is 24. The out-of-band peaking is deliberately set to help the stability and to allow larger input signals to be processed by the loop. This modulator achieves 78.2dB peak SNDR...
The high channel count of many modern communication systems increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/S with a 10MHz input. With a 200MHz input, the ADC achieves 71.0dBFS SNR, 69.4dBFS SNDR and 81dBc SFDR. The complete ADC including reference, clock, and digital circuitry...
This paper presents a VGA 1/13-inch system-on-chip (SoC), primarily targeted for the consumer camera mobile phone market. In this market low cost, ease of product integration, low module height, and low light image quality are important features. The SoC simplifies integration of the sensor into the final product by providing camera functions such as: automatic exposure control, automatic white balance,...
GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high power dissipation. An alternative is continuous-time (CT) DSP [1], which uses...
This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4...
A Frequency-to-voltage converter (FVC) for use in a system for feedback linearization of VCOs is presented. The VCO linearization is intended for use in an ADC application where high resolution, low power consumption, and low voltage operation is required. These requirements places stringent demands on the performance of the FVC. The proposed implementation of the FVC is a good fit for digital CMOS...
This paper presents the design methodology to recover charges in Analog-to-Digital Converter using adiabatic technique. Charge redistribution Successive Approximation Register (SAR) ADC is used as the main ADC architecture. The proposed ADC can operate in two modes - fast switching mode and adiabatic mode. In the fast switching mode, conventional DC supply is used and the ADC performs normal SAR ADC...
This paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However it suffers from nonlinearity, and hence needs calibration; conventional background calibration methods take a long time to...
This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm.
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