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A second-order audio sigma-delta modulator has been implemented in 40nm CMOS with 0.05mm2. Hybrid mode operation with comparator reduction technology is designed under optimized system synthesis model. DAC element selection with positive and negative state scrambling is provided in the design. A start-up sequence including RC calibration and signal monitoring is developed to prevent unstable operation...
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
A 9μW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35μm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance,...
In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 ??m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25 MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7 dB, which is 16.6-bit resolution, 103 dB dynamic range. The whole circuits consume 58.55-mW from a single...
Several low-power, single- and multi-stage ΔΣ modulators were designed in a 1.2-V 0.13-nm UMC CMOS process. The distinguishing feature of these modulators is the elimination of operational amplifiers (opamps) in the loop filters and their replacement by comparators with current sources at their outputs. These so-called comparator-based switched-capacitor (CBSC) circuits offer several advantages over...
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