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Due to the extreme complexity of neuroscience and neurosurgery, there is naturally a need for probing systems with more functions which can probe in three dimensions. For instance, nerves can size differently in different locations and can present three dimensional neuro imaging with multiple recording and stimulating points, calling for the new developments in this emerging field. It is also highly...
In this paper, four kinds of 3X3 TSV arrays in different forms of signals and grounds were modeled and simulated using Finite Element Method. The analysis was performed by ANSYS HFSS. The target of this research is to study the influence of TSV array pattern on signal transmission characteristic and to give a guide for the design of package level interconnect using TSV arrays. The simulation results...
Abstract-the 3D integration and packaging of semiconductor devices has gone through a paradigm shift over the last decade. The 3D technology outperforms conventional semiconductor assembling methods in density, cost, and performance simultaneously. This paper summarizes characteristics,platforms, approaches, and trends in 3D semiconductor optoelectronics.
Intel's Moore's Law focuses on shrinking the transistors in the silicon to be able to pack more and more transistors for a given area. In general, Intel has been able to double the transistor count every 18–24 months and has been doing so while keeping the silicon size at about the same size or even smaller. The key implication to that trend has been the I/O density that needs to be routed through...
Intel's Moore's Law focuses on shrinking the transistors in the silicon to be able to pack more and more transistors for a given area. In general, Intel has been able to double the transistor count every 18-24 months and has been doing so while keeping the silicon size at about the same size or even smaller. The key implication to that trend has been the I/O density that needs to be routed through...
The photonics packaging platform ePIXpack serves the academic community with packaging & assembly developments in the area of integrated photonics. Here we shall review the concept of ePIXpack and some of their recent work.
Rapidly growing performance and mixed-signal integration is driving the need for product component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives. Embedded capacitors are widely used for broad range of applications including filtering, tuning and power-bus decoupling in the substrate. Micro-Electron-Mechanical...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
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