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A laterally diffused metal oxide semiconductor (LDMOS) has been fabricated on a 12.2 μm buried oxide (BOX) silicon-on-insulator (SOI) substrate, successfully achieving a breakdown voltage of over 2000 V. This paper describes the proposed drift structure for SOI LDMOS. The proposed LDMOS drift structure adopts SOI reduced surface electric field (SOI RESURF) technology, which uses the BOX layer to establish...
A novel high-voltage interconnection (HVI) structure with dual trenches for 500V SOI-LIGBT is proposed in this paper. Compared with the conventional dual trenches structure, the proposed structure features a shallow trench (T1) and a deep trench (T2) beneath the HVI. By employing the shallow trench (T1), the potential can easily penetrate into the deep trench (T2) and the total potential sustained...
This study investigates the p-well/n-well junction by using secondary electron potential contrast (SEPC) with in-situ nanoprobe biasing. Experimental result demonstrated dopant contrast is restored after applying electricity in the junction nodes. Furthermore, the image contrast was converted to a voltage scale, allowing the junction surface potential and electric filed distribution to be identified...
We propose a high voltage silicon-on-insulator (SOI) LDMOS with a Buried N-layer (BN SOI) in a self-isolation SOI high-voltage integrated circuit (HVIC). The ionized donors present in the BN enhance the interface silicon field strength from 10 V/μm of the conventional P-SOI (CP SOI) to 30 V/μm. As a result the maximum electric field in the buried oxide before the adjacent SOI breaks down (named E¡)...
We report on using a single trench unit process for the trench isolation and for the trench power MOSFET of a common-drain smart power IC technology. The trench power MOSFET has a maximum specific on-resistance, (RonldrA), below 50 mOmega-mm2 and a typical breakdown voltage, Vbr, of 95 V. The trench isolation provides well isolation up to 90 V. Using a single trench unit process for both devices results...
Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
A planar edge termination technique of trenched field limiting ring is investigated by using 2-dimensional numerical analysis and simulation. The better voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
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