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3D imaging capable devices have been available on the market for a few years now and the availability of 3D contents is also picking up. However, 3D contents available for viewing is not growing fast enough to meet the demand. To compensate for such a problem, most 3D imaging devices are equipped with 2D to 3D conversion function. Also, common 3D contents available are mostly produced with 2 view...
ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of...
As fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer...
A large number of repeaters are used in the global interconnects of any System-on-Chip (SoC) design for improving the delay characteristics, and these repeaters consume a significant portion of the chip area and power. In this work we emphasize that due to increasing trend of the variability, power and area optimal repeater insertion methodologies should also consider performance variability. Analytical...
As more processing cores are integrated into one chip and the feature size continues to shrink, the increasing on-chip access latency complicates the design of the on-chip last-level cache for chip multiprocessors. At the same time, the overhead of maintaining on-chip directory cannot be ignored as the number of processing cores increasing. There is an urgent need for scalable organization of on-chip...
Power gating is one of the most effective ways to reduce leakage power by shutting off the idle blocks in a system-on-a-chip. However, a current surge occurs when the gated blocks wake up from sleep mode, causing voltage fluctuations on the power rails, which is called ground bounce effect. In this paper, input vector control method is used to reduce the ground bounce. Genetic algorithm is applied...
Network-on-Chip (NoC) is proposed to solve the communication bottleneck for multi-core SoC. Performance is one of the most critical feature of the NoC. Many different approaches have been introduced to improve the performance of NoC. However, most of them focus on the network part of NoC architecture and neglect other important parts of the system, especially the processor core part. This paper proposes...
Networks-on-Chip (NoC) architecture design faces a trade-off between different conflicting metrics. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints,...
Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract...
In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required performance. Our design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow...
To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO reduces...
We have proposed (??, ??)-based flow regulation to reduce delay and backlog bounds in SoC architectures, where ?? bounds the traffic burstiness and ?? the traffic rate. The regulation is conducted per-flow for its peak rate and traffic burstiness. In this paper, we optimize these regulation parameters in networks on chips where many flows may have conflicting regulation requirements. We formulate...
For high frequency design of SoC systems, cascaded crossbar switches become more and more popular. In this paper, we present a method based on FFT-butterfly architecture. This method can provide optimal topology of cascaded crossbar switches, which consists of multiple small crossbar switches. We apply it to AMBA3 AXI-based bus system design. Experimental results show that the proposed methods allow...
It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary...
One of the challenging problems in application-specific networks-on-chip (ASNoC) design is customizing the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. Given the application core graph, the partitioning problem is formulated as an...
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of these highly-integrated systems. Towards this modeling goal, we present a methodology for packet-level static timing analysis in NoCs. Our methodology enables quick and accurate gauging of the performance parameters of a virtual-channel...
Due to technology scaling, it is expected that future chips would integrate tens to hundreds of functional units. The growing power and design costs limit the benefit of continuously increasing the universality and complexity of these units and motivate the usage of specialized hardware modules. These modules are likely to be replicated in order to exploit the inherent parallelism of many tasks. This...
To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is proposed and optimized. We propose a signaling structure to compensate the distortion and attenuation of on-chip transmission lines, which uses passive compensation and inserts repeated transceivers composing sense amplifiers and...
To eliminate hotspots in 3D designs, physical layouts are always adjusted by shifting hot blocks. However, these modifications may degrade the packing area as well as microprocessor performance greatly. Furthermore, to improve time-to-market via design cycle reduction, incremental design must move from an expert methodology to a mainstream design methodology: one that is automated, integrated, reliable,...
Multimedia and computational intensive applications are more and more pushing towards high-performance, low-power consumption and limited area occupation making the concept of optimality multi-objective. In the context of a design space exploration framework to support the platform-based design approach, we address the problem of robust optimization of a parameterized system-on-chip platform towards...
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