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In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for...
In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software...
This paper presents our parallelization and implementation of the ORTHOMIN solver on the Cell Broadband Engine. The solution of linear systems of equation sis one of the most central processing unit-intensive steps in many engineering and simulation applications and can greatly benefit from the multitude of SIMD-capable synergistic processor element (SPE) cores in the Cell processor. We report the...
A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling...
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application...
This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and...
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements...
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part...
This paper describes a self-configurable middleware and a node execution platform to support autonomous sensor networks. We achieve self-configuration by scheduling and strategies similar to load balancing (mapping) that is integrated in our proposed middleware. On the node execution platform we decide on the fly between microprocessor and FPGA realization of hybrid tasks. We propose a combination...
MMP16 stands for 16-bit Didactic Micro-Programmed Micro-Processor and consists in a comprehensive learning tool for those students of electric engineering and related disciplines that, having studied the basics of digital electronics, need to understand the principles of computer organization prior to study advanced computer architecture. Therefore, MMP16 has been designed as a bridge between the...
In general, the Less Recently Used (LRU) policy was commonly employed to manage shared L2 cache in Chip Multiprocessors. However, LRU policy remains some deficiencies based on previous studies. In particular, LRU may perform considerably bad when the workloads of application program are larger than L2 cache, because there are usually a great number of less reused lines that are never reused or reused...
On a CMP (Chip Multi-Processor) architecture, cache sharing impacts threads non-uniformly, where some threads may be slowed down significantly, while others are not. This may cause severe performance problems such as throughput decreasing, cache thrashing. This paper proposes an architectural support predicting method (ASPM) to predict inter-thread cache contention, and schedules threads based on...
Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
High temperatures and non-uniform temperature distributions have become a serious concern since they limit both performance and reliability of Integrated Circuits (IC). With computer architect's concern to position microarchitecture blocks in a processor, faster thermal models can be developed at the cost of hiding finer grain details such as circuit or transistor level information. Several methods...
The recent spectacular progress in modern Nan electronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. The increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
As Chip Multiprocessors (CMPs) scale to tens or hundreds of nodes, the interconnect becomes a significant factor in cost, energy consumption and performance. Recent work has explored many design tradeoffs for networks-on-chip (NoCs) with novel router architectures to reduce hardware cost. In particular, recent work proposes bufferless deflection routing to eliminate router buffers. The high cost of...
To date dynamic voltage/frequency scaling (DVFS) has been one of the most successful power-reduction techniques. However, ever-increasing process variability reduces the reliability of static random access memory (SRAM) at low voltages. This limits voltage scaling to a minimum operating voltage (VDDMIN). Larger SRAM cells, that are less sensitive to process variability, allow the use of lower VDDMIN...
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