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This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an...
This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability...
Approximate probabilistic model checking, and more generally sampling based model checking methods, proceed by drawing independent executions of a given model and by checking a temporal formula on these executions. In theory, these methods can be easily massively parallelized, but in practice one has to consider, for this purpose, important aspects such as the communication paradigm, the physical...
Reliability is becoming an important feature of digital circuits implemented on deep submicron technologies. Fault tolerance techniques can be used in order to improve the circuit's reliability but leading to some kind of design penalties (area, time, power consumption). In this work, we propose a method that takes into account reliability and other classic design parameters when choosing the most...
On the basis of mounting LCD, VGA and PS/2 mouse to the Avalon bus, the paper ports μC/GUI to the LCD in the system based on Nios II. It also creatively ports Mu-C/GUI to the VGA display, and implements feature of supporting PS/2 mouse. These effectively solve the problem of human-machine interface in Nios II system.
Embedded systems designers frequently avoid using floating-point computation because it is too costly to include a floating-point unit (FPU) in an embedded processor. However, the performance of software floating-point libraries can be lacking. Therefore we propose a fractured floating point unit (FFPU)-a hybrid solution using a mix of custom hardware instructions and software code. An FFPU is designed...
One of the most widely used schemes to extract feature points suitable for tracking in computer vision is "good features to track''. In this paper, we propose parallel implementation of the good feature extraction scheme optimized for the cell processor, which is one of the latest high performance embedded processors. By utilizing the computational power of cell suitable for image processing,...
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and being able to reuse legacy code are real challenges for application developers. We propose to use Generative Programming and more precisely template meta-programming to design an domain specific embedded language using algorithmic...
This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can...
This paper explores the usefulness of the Sony PlayStation 3reg(PS3) for medical image processing. Medical image processing often entails dealing with a large number of high resolution images, requiring a large amount of computational power to process. The PS3 is powered by the cell broadband engine, a microprocessor created by IBM, capable of rapid numeric computation with low power requirements...
Few realize that for large matrices dense matrix computations achieve nearly the same performance when the matrices are stored on disk as when they are stored in a very large main memory. Similarly, few realize that, given the right programming abstractions, coding Out-of-Core (OOC) implementations of dense linear algebra operations (where data resides on disk and has to be explicitly moved in and...
In this paper we present a framework for implementing computer vision algorithms on embedded processors using the analog devices Blackfin BF561 processor. This framework is designed to consist of a set of simple functions that allow complex tasks to be performed, such as object tracking or object recognition. Special consideration is given to the methods of optimization that are needed to achieve...
In the paper, we investigate the memory access technology on cell broadband engine architecture (CBEA), and develop a profiling infrastructure for memory management on the architecture. By registering the dynamic memory allocation and providing details of trace of memory access, the infrastructure provides the data partition information automatically which alleviates the burdens of programmer and...
This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90...
Computer architecture science evolves continuously. This work describes a methodology to teach a system which is integrated by several processors in just one chip. The description of how to implement a biprocessor system within an FPGA is proposed. Thus, the student will simultaneously acquire advanced knowledge on microprocessors, focusing on the operational behavior and structure of a biprocessor...
This paper presents a self-testing framework targeting the LEON3 embedded microprocessor with built-in test-scheduling features. The proposed design exploits existing post production test sets, designed for software-based testing of embedded microprocessors. The framework also includes a constraint-based approach of test-routine scheduling. The initial results show that the test execution time could...
The single-chip multi-processor system, which uses the technique of parallel processing, can well improve the performance and processing ability of the CPU. This paper proposes a method of parallel processing based on the task library, and presents a strategy about task distribution and scheduling. It has been implemented by hardware and the verification about task loading and task scheduling has...
Is real-world gaming technology the next big thing in the more academically based high-performance computing arena? The authors put PlayStation 3 to the test.
Embedded web servers have a growing presence in a wide range of fields related to consumer electronics and industrial applications. FPGAs are a valid alternative in the implementation of these systems adding additional advantages to the traditional architectures based on microprocessors or microcontrollers. In this paper we introduce two web server implementations on FPGA devices. The first uses an...
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