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The method of Graph Cuts converts a Maximum a Posteriori (MAP) inference problem on a Markov Random Field (MRF) into a network flow, which can be solved efficiently. Many computer vision problems can be conveniently cast as an inference task to find most likely labels for pixels. The method is widely used, but computationally burdensome. Prior accelerator attempts have failed to exploit the problem's...
The paper discusses fault diagnosis of the electronic circuit board, part of acousto–magnetic electronic article surveillance detection devices. The aim is that the end-user can run the fault diagnosis in real time using a portable FPGA-based platform so as to gain insight into the failures that have occurred.
This article describes a prototype FPGA implementation, of a delay-and-sum beamformer in the audio frequency range. This prototype is essentially a real-time acoustic camera, which is used to estimate a sound field intensity. Data acquisition is performed by means of a 4-microphone square array and the delay- and-sum beamforming algorithm is implemented on a Xilinx Spartan 3AN FPGA. The computed acoustic...
Electronically scanned digital antenna array apertures have important applications in ultra-wideband digital beamsteering for cognitive radio, imaging, radio astronomy, wireless communications and sensing. The use of 2-D IIR frequency-planar beam plane-wave filters as a low complexity alternative for phased array algorithms is currently receiving attention. In this work, a systolic array VLSI architectures...
In this paper, we propose a microphone array network that realizes ubiquitous sound acquisition for multiple sound sources. Several nodes with 16 microphones are connected to form a huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and enhancement. The three operations are distributed among nodes with multi-hop data communication. Using the...
Networks-on-chip (NoC) are very efficient for point-to-point communication but are also known to provide poor broadcast and multicast performance. In this paper, we propose a triple hybrid interconnect for many-cores, consisting of a reconfigurable mesh network and a wormhole routed NoC for data communication, and a barrier network for synchronization. On an FPGA many-core prototype comprising up...
The real-time acoustic camera prototype. consists of a field-programmable gate array (FPGA) base-board and an A/D-conversion board with 32 attached microphone modules arranged in a rectangular array. The FPGA base-board is connected to an external TFT display. Two loudspeakers will be connected to a laptop and play audio test-signals. The external display visualizes the location and intensity of the...
Acoustic cameras visualize the origin and intensity of sound waves using an array of microphones and sophisticated signal-processing algorithms. Due to the high memory-bandwidth and signal-processing complexity required by such algorithms, current available devices either compute the corresponding intensity-images off-line or require large and expensive hardware equipment. In this paper, we describe...
This paper presents a demonstration on various grayscale and binary processing operations performed in real-time on the MIPA4k array processor prototype system. The emphasis of the demonstration is on asynchronous wave propagation operations in both grayscale and binary domains and a related object segmentation and tracking algorithm discussed. However, also the functionalities proposed in the other...
This paper presents an implementation of analogue baseband beam steering and its digital counterpart as an attempt to compare between both methods for LEO satellite applications. Both methods are explained, implemented and compared in terms of different aspects such as power consumption, space qualification, flexibility, and speed of steering for a 1×2 prototype.
This paper describes a sparse priority queue suitable for reporting the results from a sequence database search, using a self-timed protocol. The prioritization is simplified through an insertion sort scheme with no greater/less than logic. The resulting implementation promises to be compact, fast, and suitable for the specified application area. The architectural design has been validated on a prototype...
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
The reconfigurable mesh model for massively parallel computing has recently been rediscovered and proposed as the basis of a practical many-core architecture. With this paper, we are the first to study the power and energy requirements of reconfigurable meshes. We present two methods to reduce the power consumption, exploiting characteristics of typical reconfigurable mesh algorithms. We extend our...
A digital array radar system prototype is presented that makes use of a hierarchical digital backend coupled with highly-integrated, multi-channel RF transceivers. The general benefits of using such a hierarchical architecture are briefly discussed, along with how this prototype is in line with a vision for future radars that fully embrace the concept of low-cost integration in a panelized platform...
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