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Bit matrix compression is a highly relevant operation in computer arithmetic. Essentially being a multi-operand addition, it is the key operation behind fast multiplication and many higher-level operations such as multiply-accumulate, the computation of the dot product or the implementation of FIR filters. Compressor implementations have been constantly evolving for greater efficiency both in general...
Objective: To implement an algorithm for improving the speed of Floating Point Multiplication. Methods/Statistical analysis: Recursive Dadda algorithm is used for implementing the floating point multiplier. IEEE 754 single precision binary floating point representation is used for representing Floating Point number. For the multiplication of mantissa Carry Save multiplier is replaced by Dadda multiplier...
This paper presents XtokaxtikoX, a fully autonomous cyber-physical system employing only stochastic arithmetic to perform computations on its data-path. Traditional implementations of stochastic computing systems benefit from fast and compact implementation of arithmetic operators, and high tolerance to errors, but depend heavily on the conversion between stochastic bitstreams and binary to implement...
Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Prior work on GPC synthesis using FPGAs has focused on utilizing the fast carry chain and mapping the logic onto LUTs. This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. Modern day Xilinx FPGAs support 6-input LUTs that can be used...
This work studies implementations of the Perception [1] and TAGE [2] branch predictors for general purpose, in-order pipelined single core soft processors. It proposes FPGA-friendly optimizations whose goal is to achieve high operating frequency. This work discusses the design tradeoffs and proposes a highly accurate and fast branch predictor variant based on TAGE, O-TAGE-SC. It operates at 270MHz,...
Fast multipliers are essential for many applications such as digital signal processing (DSP) and image and video processing. Tree parallel multipliers are the fastest ones. The only disadvantage of tree multipliers over serial multipliers is its high cost in terms of area and power dissipation. In this paper, we present a new efficient reduction scheme to implement tree multipliers on field programmable...
An antilog is the inverse function of a logarithm. Today, conventional use of the term “antilog” has been replaced in mathematics by the term “exponent”. The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system...
Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. This can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting...
Productivity for digital circuit design is being outpaced by the rate at which silicon is growing. Complex designs take a significant amount of engineering hours to complete in both ASICs and FPGAs. Design reuse can potentially decrease cost and increase design productivity. The central thesis of this paper is that design productivity could be enhanced by assisting the designer in discovering archived...
Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant...
Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.
Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power...
This paper deals with more efficient and effective way of handling the random and busy traffic pattern on Indian roads. The purpose of this paper is to flush out the concept of nondynamic traffic light controller TLC (with fixed counters irrespective of traffic intensity) existing in INDIA and other developing nations. This AD-TLC concept will save time and will smoothen the traffic flow by avoiding...
In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable...
We show that there is significant benefit to using a reconfigurable computer to enumerate bent Boolean functions for cryptographic applications. Bent functions are rare, and the only known way to generate all bent functions is by a sieve technique in which many prospective functions are tested. The speed-up achieved depends on the number of variables n; for n = 8, we show that the reconfigurable computer...
We evaluate some of the previously proposed test algorithms and approaches for various types of multipliers. We present methods to effectively test multipliers independent of their architecture and to achieve greater than 99% single stuck-at gate-level fault coverage with a simple 8-bit or 9-bit binary up-counter and some multiplexers. Finally, we discuss testing the multipliers present in most current...
This paper proposes a simple but practical Gaussian-distributed pseudo-random number generator. The features of this generator include a compact architecture based on a decimator connected linear feedback shift register, Gaussian-distributed N-bit random number output, long period of a random number sequence, and good statistical properties.
Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on...
Recent FPGA architectures facilitate the efficient mapping of high order compressors to implement multi-operand additions. This feature can be used to improve the performance and area utilization of large size multipliers. In this paper we present an improved design approach utilizing ternary adders and Generalized Parallel Compressors, GPCs, for the addition of the partial products. Multipliers of...
We propose a new DSP block for use in modern high-performance FPGAs. Current DSP blocks contain fixed-bitwidth multipliers that can be combined efficiently to form larger multipliers. Our approach is similar, but includes a bypass layer following the partial product generator that exposes the compressor tree used for partial product reduction directly to the user. As a consequence, the proposed DSP...
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