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A model of input data buffering in measuring systems is developed. The authors obtained the formulae to determine the following time intervals: between two successive transactions to signal source, two successive transactions to signal receiver, between transactions on data receiving and generation, between transactions on data generation and receiving. It is shown that an adequate model of the buffered...
Complex low power integrated circuits use global power management strategies to orchestrate the switching between power states of multiple power domains. One of the primary challenges in verifying such power management architectures stems from the mixed implementation of such strategies, where the local power controllers are in hardware and the global power management is implemented in software/firmware...
In digital communication systems, application of chaotic signals offers several advantages. One of the most important advantages is increased security which is due to their noise-like and broad spectrum characteristics. In order to find an efficient way for chaotic system synchronization and secure communications this paper combines chaotic masking and chaotic modulation encryptions. The proposed...
This paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching...
In this paper we present for the first time a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating...
GALS Networks-on-Chip (NoCs) in which the frequency of every switch can be set independently would enable per-node DVFS without requiring asynchronous switch design. However, traditional GALS interfaces introduce high latency penalties and are therefore ill-suited for inter-switch links in a NoC. In this paper we introduce and study a GALS Network-on-Chip based on the Globally-Ratiochronous, Locally-Synchronous...
A number of methods have been proposed for synchronizing chaotic systems. The most widely used methods are continuous synchronization schemes. In a continuous synchronization scheme, chaotic systems are coupled to each other continuously such that synchronization errors converge to zero. In this paper, chaos synchronization in coupled discrete-time dynamical systems is presented. Simulation results...
In this paper, two chaos-based communication schemes to transmit encrypted information are presented. We use Generalized Hamiltonian forms approach to synchronize two unidirectionally coupled n-scrolls chaotic attractors. First, a scheme is set-up to transmit binary signals by applying chaotic switching technique. Both coupling signal and confidential message are send by only one transmission channel...
Power consumption in VLSI circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. However, a growing class of applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used for these applications. Unfortunately, sub-threshold circuits exhibit an exponential sensitivity to process, voltage...
We propose QUEST (QUality ESTimation), a new method that accurately estimates IEEE 802.11 wireless link quality with no in-band signaling overhead. Existing link quality estimation methods either are based on hello exchanges by fixing or varying transmission rates or rely on the history (e.g., delivery ratio) of previously sent data packets in a per-rate/-neighbor manner. QUEST on the other hand,...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
This contribution addresses the case when live packet-switched video is used to enrich circuit-switched speech calls in mobile telephony. Circuit-switched and packet-switched transmissions generally operate on completely different transmission paths resulting in different QoS in terms of delay and loss rates. In this case, video and audio data recorded at the same time are not multiplexed together...
A one chip 16??16 digital switch is presented, designed for use in a wide variety of applications, ranging from digital mobile radio and satellite applications, to PCM switching systems (ISDN). It provides a compact, low power solution to perform in channel controlled switching of 64 kbit/s or 2 Mbit/s channels. Architecture and design examples are discussed in detail.
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