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Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64χ inter leaved 2...
The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet...
A fully CMOS transmitter including a power amplifier (PA) using a Cartesian Feedback (CFB) technique is presented. This system aims at improving the linearity of the transmitter, designed in 65nm CMOS technology from STMicroelectronics, essentially the power amplifier linearity. This transmitter delivers a maximum output power of 23dBm. Thanks to this linearization technique, the ACPR has been improved...
This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
In this paper we propose a variable-gain transimpedance amplifier suitable for low-power applications. Its noise, bandwidth and input impedance performance are similar to a more conventional regulated-cascode common-gate transimpedance with resistive load, with the same power consumption and gain performance. The proposed amplifier has, however, variable gain, which can be easily changed by setting...
A 3-GS/s 5-bit flash ADC is fabricated for millimeter-wave communication systems in 65nm CMOS technology. The proposed foreground calibration method reduces the input-referred DC offset, achieving the resolution of 4.7 ENOB at 200MHz input frequency and keeping more than 4.3 ENOB even at Nyquist. The ADC consumes only 36.2mW including the power of the clock buffer and the resistor ladder from 1-V...
A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved...
A 300MHz all-digital differential VCO-based ADC occupies 0.02mm2 in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.
We present an integrated 900MHz receiver with 56.4dB conversion gain, 5dB NF, and -9.8dBm IIP3 using on-chip in-band feed-forward interference cancellation. The interference cancellation at baseband gives more than 13dB IIP3 improvement and makes operation from an ultra-low 0.6V supply possible. The direct-conversion receiver including baseband filters and polyphase LO filters and buffers consumes...
In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver...
In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1st stage has a 1.5b resolution architecture, the remaining stages have 2.5 b resolution architecture...
A direct down conversion Gilbert-type mixer in combination with an active low-pass filter for 4MHz is presented. The Gilbert-type mixer is enhanced with a source degeneration to improve the linearity performance. The active filter is a linearity enhanced differential amplifier with feedback network. For the high supply voltage of 2.5V additional over-voltage protection with cascodes is added to the...
A 4th-order continuous-time band-pass filter for wireless receivers is here presented. The filter is composed by the cascade of two active RC cells. The overall pass-band (32 dB) gain is distributed for each cell in order to minimize the power consumption. The operating point issues due to the low VDD/VTH ratio - a value of 2 is typical in CMOS 65 nm technologies and down - have been solved by adding...
An LNA with integrated Q-enhanced notch filter for use in FDD transceiver systems has been demonstrated. The amplifier core is coil less, made possible by the use of capacitive shunt-series feedback to simplify matching. Additionally, a Q-enhanced notch filter is integrated which attenuates TX blockers thus making an external interstage SAW filter redundant. A prototype was produced on a 65 nm CMOS...
This paper reports a new programmable Gm-C-OTA integrator and filter, which allows on-chip periodic analog signal generation and in essence, fulfils the function of the D/A converter. The method has the attributes of digital programming and control capability, robustness and reduced area overhead, which make it suitable for built-in self-test applications. The circuit has been fabricated in standard...
A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm" value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad...
A wideband receiver for cognitive radio spectrum sensing unit is presented. The circuit consists of a high linearity low noise amplifier, passive mixer, and baseband buffer. IQ signals for the LO are generated using a divide-by-two circuit. Low noise amplifier includes common-gate common-source combination for simultaneous interference suppression and noise canceling. The receiver operates in the...
This paper presents the design of a fully integrated inductorless wideband RF front-end for wireless applications including WLAN, Bluetooth and UWB. The core of the circuit is comprised of a two stage LNA, followed by a standard Gilbert cell mixer and an output buffer for measurement purposes. The chip was fabricated in 65 nm standard CMOS process. The RX offers an input matching of better than -10...
Limit-cycle amplifiers have shown promising potentials for linear and efficient amplification of high crest-factor signals. In this paper, the efficiency of a class-D amplifier in a limit cycle loop has been evaluated for a random Gaussian input in terms of the input power level, limit cycle amplitude and output load admittance. Multisine representation of the Gaussian signal has been used to calculate...
We describe a new outphasing transmitter architecture in which the supply voltage for each PA can switch among multiple levels. It is based on a new asymmetric multilevel outphasing (AMO) modulation technique which increases overall efficiency over a much wider output power range than the standard LINC system while maintaining high linearity. For demonstration, the overall transmitter is simulated...
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