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Nano-grain reconfigurable cells have the potential to replace memory-consuming LUT (Look-Up Table). However, the cells offering the highest area improvement are also those offering the lowest flexibility, i.e. not all the Boolean functions are available. Reaching the same flexibility of LUT is mandatory to reuse existing FPGA tool flows, which can be obtained by clustering cells in a matrix-like architecture...
This paper reviews the use of UHF double class-E (class-E2) topologies for dc/dc power conversion. After introducing this attractive resonant converter in the context of the time-reversal duality principle, two different lumped-element networks are described for appropriately terminating the drain of the switching devices. Recent implementation examples, taking advantage of GaN HEMT processes, are...
This paper presents a comparative study on high-frequency active rectifier-based zero voltage soft-switching (ZVS) resonant dc-dc power converters with Gallium Nitride Heterojunction-Field-Effect-Transistor (GaN-HFET) for inductive power transfer (IPT) systems. The two types of active rectifiers, i.e. high-frequency bridgeless rectifier (BLREC) and totem-pole rectifier (TPREC) are adopted for the...
Z-source inverters (ZSIs), compared to the conventional two-stage architecture, embrace some interesting features, like the reduced size and complexity of the entire conversion system. Many research activities have been established to improve the performance of the so-called ZSI since it has been proposed in 2003, and several modifications have been introduced since then. These modifications include...
This paper presents a selective harmonics reduction for a 3(n+1) shared switch inverter topology utilizing optimal arrangement of the n-modulated signal. Under different modulation indices and operating power frequencies the purpose of the proposed procedure is to select an optimal load connection and/or modulation offsetting based on the desired objective function. Three performance indices are studied...
An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
In Software Defined Networking (SDN), connections between the controller and the switches are maintained in two ways: out-of-band and in-band. In out-of-band controlling, the control channels are constructed via separate links. However, due to several reasons, sometimes in-band controlling is needed instead of out-of-band controlling. In in-band controlling, the data paths are used for control channels...
In this paper, we have explored the impact of different gate architectures in controlling short channel effects in scaled AlGaN/GaN HEMT devices using calibrated 2-D TCAD simulations. Devices with different gate topologies, namely I-Gate and T-Gate are investigated for their efficacy in minimizing the short channel effects. Various parameters like transconductance, channel conductance and drain induced...
In this paper, we present a simple differential CMOS ISFET based pH sensor. The design uses two different sensing areas. The resulting sensor reduces complexity and power consumption making it suitable for implantable biomedical applications. The design is implemented in a standard 130nm process and the design constraints on sensitivity are explored. Analytical results based on theory show that sensor...
The field of wireless sensor networks is progressing at a very rapid pace with one of its major application in the area of agriculture. Several research problems have been addressed and solutions have been proposed. Most of these works are based on single crop scenario. Research done in the multiple-cropping scenario, where two or more crops are sown in a single field in the same year, are very few...
We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification...
The paper proposes a method to synthesize a digital controller for multiphase switched capacitor converters (SCCs). A specific requirement to the controller is that, regardless of external conditions, it should provide pulses of fixed frequency and width. Asynchronous (self-timed) digital circuits fulfil this requirement by definition. However, their design can be quite complex, especially if an SCC...
A novel topology for LED drivers is proposed. The system does not require rectifier input stage nor storage DC bus capacitor. The topology is described and studied by simulation. Experimental results on an AC LED demonstrator using GaN transistors validate the proposed circuit.
The performance of a Modular Multilevel Converter (MMC) is presented in this paper, comparing Silicon (Si) and Gallium Nitride (GaN) semiconductors. Moreover, the benefits of high-frequency operation in a MMC topology are analysed along with a power loss distribution evaluation, highlighting the main advantages and drawbacks of different semiconductor technologies.
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
Interfacing techniques for near-threshold computing are described in this paper. A bi-directional input/output circuit with integrated level shifters is proposed for multiple near-threshold power domains. The circuit provides conversion ranges of 0.38 V to 1.2 V and 0.45 V to 3.3 V depending on the targeted output voltage. Eight different configurations of I/O circuits are evaluated with level shifters...
3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
An improved readout circuit interface for ion-sensitive field-effect transistor (ISFET) is proposed in this work. When compared with conventional topologies found on the literature, the proposed ISFET readout circuit presents at least two advantages. The first concerns the simplicity of the new circuity topology, and the second is the additional gain conferred to the sensor output signal. The performance...
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