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We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification...
Layout design principles of IP blocks in the IC, and frequency mixers in particular, are discussed. Several variants of the layout design are carried out. They are modeled and compared to a schematic implementation. Qualitative assessment of implementations is carried out. The conclusions and the ways of improvement are proposed. The nature and the origin of deviations and variations in the process...
Several topologies of high voltage input DC/DC power supply are investigated firstly in this paper and then a novel gate control strategy for cascade SiC MOSFET stack using a single standard gate driver is proposed. Thereafter, operation principles including both static sate and switching transitions are analyzed. The LTspice simulation results validate the analysis and show the availability of the...
The current automotive IC sector counts hundreds of different systems, standard products or ASICs, for the inductive load drivers application. Many of them, such injector drivers, DC/brushless motor drivers, solenoid drivers, are designed to work in a specific operating mode, with fixed architecture and parameters. Since the need of different applications increases, a flexible approach to the design...
Wide-bandgap power switches, based on SiC and GaN, are emerging on the semiconductor market. Standard resistor drivers are insufficient to exploit all the advantages of these new devices. Fine control over current and voltage waveforms during switching, equivalent on-state resistance and immunity to noisy environments, demand the development of dedicated drivers. This study aims at determining a suitable...
This paper concerns the design and the implementation of a transimpedance amplifier (TIA) dedicated to detector of Near Infrared spectroscopy (NIRS). To reduce the effect of the input capacitance on the bandwidth, a bias circuit with low input impedance is connected to input stage. A single ended common source common gate input stage based on a cascode structure is used to get a higher gain bandwidth...
A 24-segment current-steering transmitter with 3-tap pre-emphasis and linear auto-tuned active line terminations is presented. A linearized resistor-MOSFET termination structure for continuous impedance tuning is proposed to maintain an accurate output voltage level (σ=1%) and good impedance matching (σ=2%). This enables larger signal drive strengths thanks to more efficient supply utilization. The...
In this paper, we present a comparison of high-voltage linear transmitter circuits for driving capacitive micro-machined ultrasound transducers (CMUTs). CMUTs are emerging transducer elements in ultrasound imaging applications. Two different circuit topologies for the high-voltage linear transmitter with a 40 V peak-to-peak output voltage are compared. We compare the two designs based on total harmonic...
This paper presents design approaches focused on application of amplifiers structures in High-voltage technology processes with special regards to Silicon-on-Insulator ones. Voltage-mode and current-mode approaches are taken into account and implemented. The presented topologies are discussed and HV application potential of current-mode is pointed out.
This paper presents ways of enable and power-down functionality implementation in HV SoI buffers. Several HV buffer topologies are taken into account. Power-down, high input and output impedance functionality implementation approaches are presented and discussed.
Four novel compact differential pair (DP) topologies with enhanced transconductance gain are introduced: direct positive feedback DP, quasi floating gate DP, floating gate DP and tunable quasi floating gate DP. All of them use positive feedback to achieve gm enhancement and have the same supply requirements as the conventional differential pair. Results for 0.13 μm CMOS designs supplied at 1.0 V show...
Verification of net-oriented ESD rules is rapidly becoming critical for nanometer design. To meet chip-level complexity and size challenges, a novel approach using topology-aware net types is developed to enable fast, hierarchical verification. This is applied to ESD design rules for power/ground interfaces and successfully adopted in production verification flows.
After a brief reminder of standards concerning power efficiency both for active or standby modes, we present some experimental results of standby losses for various AC-DC power supplies used in appliances. Then we explain how to reduce the power supply rating by reducing the current demand to control AC switches used in this kind of device. Finally, we introduce a compressor starter application where...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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