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A Public Key Infrastructure (PKI) is based on a trust model defined by the original X.509 standard and is composed of three entities: the Certification Authority, the certificate holder (subject) and the Relying Party. The CA plays the role of a trusted third party between the subject and the RP. A trust evaluation problem is raised when an RP receives a certificate from an unknown subject that is...
This paper presents a comparison of standard topologies for AC-DC converters within micropower energy harvesting systems. The focus is on low input voltage (< 1 V), low input frequency (< a few kilohertz), ultra-low power consumption (nanowatts to microwatts), and fully integrated inductor-less cold start topologies. These standard topologies are compared in terms of PCE (power conversion efficiency),...
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary...
This paper presents topological constraints of gate-level circuits obtained through standard cell recognition applied to gate-level commercial microelectronics verification. A suite of topological constraints, including the gate vertex count, net vertex count, terminal count, blocks, circuit genus, Euler characteristic, and number of faces are extracted from gate-level circuits obtained through standard...
Adders are the logic circuits designed to perform these arithmetic operations at a high speed. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. An approach that locates the design's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which...
The authors of this paper explore the use of IPv6 over Low power Wireless Personal Area Networks (6LoWPAN), IPv6 Routing Protocol for Low power and Lossy Networks (RPL) and Constrained Application Protocol (CoAP) as a possible solution for realising the Internet of Things (IOT) vision in Industrial Wireless Sensor Networks (IWSNs), The aim of this paper is to investigate the feasibility of using Internet...
This paper introduces a new way of monitoring critical parameters directly inside circuits. It describes a flow able to transform a circuit into a test vehicle: the concept is called topological exchange. The principle is to remap existing standard cells to create monitoring functions. The flow is detailed through a specific example of oxide thickness monitoring and the method is validated with post-layout...
Over the last decade the wireless technology has gained interest in process automation world due to its cost effectiveness, rapid deployment and flexibility features. However, the deployment of wireless technology in industrial environment demands same integration approach as compared to traditional wired device integration. This is one of the important aspects which is required to be considered for...
Ethernet is by now the most adopted bus for fast digital communications in many environments, from household entertainment to PLC robotics in industrial assembly lines. Even in automotive industry, the interest in this technology is increasingly growing, pushed forward by much research and basically by the need of high throughput that high dynamics distributed control demands. This paper deals with...
As distributed energy resources are growing in number it becomes increasingly important to efficiently integrate them in a communication network to monitor and control them. Many envision IEC 61850 to be the best communication solution in this field. But the standard is still far from a plug and play setup. One step in this direction is the modeling of vendor independent IEC 61850 profiles for different...
In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence...
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