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Research in reversible computing has gained importance because of its potential use in low-power design, and also quantum computing. Several works on reversible circuit testing have also been reported. Many fault models have been proposed, some of which have been borrowed from traditional logic. In this paper, we consider the problem of reversible circuit testing, specifically targeting test generation...
Reliability testing has become extremely important in modern electronics as the soft error rate has been increasing due to technology scaling. The testing must be controllable, generic, done before deployment, cheap, and fast. Even though fault injection is often the most appropriate solution considering these requirements, it is very time-consuming. This work proposes a hybrid fault injection framework...
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
The ITC'97 analog and mixed-signal (A/MS) benchmark circuits have been available for two decades. This paper discusses why they were useful but not for comparing A/MS design-for-test (DFT) techniques, tests, or fault coverage. First, this paper discusses these and other benchmark circuits, and proposes objectives for better benchmark circuits. The paper then describes the first, publicly-available...
To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX...
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
This paper presents a physical-aware diagnosis technique for failing dies with multiple interconnect defects, including open and bridging. Our diagnosis technique considers fault masking/reinforcement and Byzantine effects. We use a section, a piece of interconnect, as the physical-aware diagnosis unit. We adopt the Single Location in a Cluster (SLIC) technique, where sections with similar simulation...
This paper presents the design and implementation of a fault simulator for the TRAnsition-X fault model (TRAX for short) on a graphics processing unit (GPU). Fault dictionaries are an important aspect of on-chip fault detection and diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. The inherent parallelism of the...
This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the...
The problems of IC reliability are now becoming increasingly important. The idea of reliability is a complex integrated concept and includes structural, schematic and technological solutions, as well as solutions at the level of logic gates, register transmissions and microsystem as a whole. This paper is devoted to preprocessing of logical circuits aimed at the reduction of computational costs of...
Susceptibility of modern ICs to radiation-induced faults constitutes a matter of great concern in the recent years. Particularly, the transient faults and their impact on the combinational logic remain an intriguing issue, since the evaluation of their behavior is quite significant, especially for critical systems, for the development of error-resistant techniques in design process. For an accurate...
In the recent years, Approximate Computing (AxC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AxC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specifications can provide significant gains in area, performances and energy...
Aliasing in the test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing generally require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc.We propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing...
Ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties. In this paper, we introduce a novel methodology to estimate the vulnerability of sequential circuits to soft errors at gate level. A new probabilistic modeling of SET propagation is proposed, which reduces the complexity of unrolling sequential circuits. This approach enables a multi-cycle error propagation...
Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits. Our approach uses a signal probability analysis to score and rank potential fault locations. The ranking results are exploited to reduce the search space for exact diagnosis approaches. The experimental results show...
As fabricated chips get larger and denser, more kinds of defects happen that cannot be explained by the traditional stuck-at-fault model. In this paper, we propose a new approach for diagnosis of bridging faults based on analysis of the logic design. The proposed approach is based on iteratively solving SAT problems until finding the internal signals that can explain the misbehavior of the circuit...
With the ever increasing process variability in recent technology nodes, path delay fault testing of digital integrated circuits has become a major challenge. A randomly chosen long path often has no robust test and many of the existing non-robust tests are likely invalidated by process variations. To generate path delay fault tests that are more tolerant towards process variations, the delay test...
Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional...
In order to make the circuit fault diagnosis system more intelligent, efficient. IsDS decision algorithm is presented based on the process of model-based diagnosis. Model-based circuit fault diagnosis system is designed and realized with SAT solvers by means of applying IsDS decision algorithm and combining CSSE-tree method. Firstly the normal behavior, system mo del and obtained observations are...
With the ever increasing size of today's Very-Large-Scale-Integration (VLSI) designs new approaches for test pattern generation become more and more popular. One of the best known methods is SAT-based automatic test pattern generation (ATPG) which, in contrast to classical structural ATPG, first generates a mathematical representation of the problem in form of a Boolean formula. A specialized solver...
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