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Research in reversible computing has gained importance because of its potential use in low-power design, and also quantum computing. Several works on reversible circuit testing have also been reported. Many fault models have been proposed, some of which have been borrowed from traditional logic. In this paper, we consider the problem of reversible circuit testing, specifically targeting test generation...
Most existing concepts for hardware implementation of reversible computing invoke an adiabatic computing paradigm, in which individual degrees of freedom (e.g., node voltages) are synchronously transformed under the influence of externally- supplied driving signals. But distributing these "power/clock" signals to all gates within a design while efficiently recovering their energy is difficult...
Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the...
Reliability testing has become extremely important in modern electronics as the soft error rate has been increasing due to technology scaling. The testing must be controllable, generic, done before deployment, cheap, and fast. Even though fault injection is often the most appropriate solution considering these requirements, it is very time-consuming. This work proposes a hybrid fault injection framework...
In this work a model of the oscillator with inductive coupling of the gates operating at ultralow voltage is presented and experimentally verified. The topology needs a bias voltage at the gates, and we propose a circuit called starting block to generate this voltage from the supply. Theoretical behavior is compared with experimental results, showing good agreement. The circuit, which behaves as astable...
Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin...
This article presents a substantial review of nonlinear memristive circuits based on Zdenek BIOLEK model alonside an innovator design developed within the Hewlett-Packard laboratories. HP realized a physical implementation of memristors by placing two layers of titanium dioxide between two electrodes. The first layer is partially doped with oxygen gaps and behaves like a semiconductor and the second...
The paper presents a comprehensive charge modelling approach for field-effect transistor (FET) devices. For the first time an artificial neural network (ANN) is combined with the division-by-current approach to FET charge modelling. Using this technique a large-signal charge model is extracted for a 10 W GaN device from MACOM. It is shown through measurements that excellent results may be obtained...
This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to...
SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high...
Silicon carbide (SiC) MOSFETs have been widely studied in high frequency applications. The switching performance, however, is limited with the existence of the parasitic elements. One critical issue is the susceptibility of the gate-source voltage to the parasitic elements, rendering the possibility of spurious operation of the SiC MOSFETs. This paper conducts comprehensive investigations on the impact...
This work deals with the implementation and development of a PSpice based modeling platform for 10 kV/100 A SiC MOSFET power modules. The studied SiC MOSFET power module is composed of a total of 9 dies connected in parallel with 10.0 kV blocking voltage capability. The proposed model was implemented based on the already established McNutt Hefner model originally developed for discrete single-die...
The limits of the current electronic solutions restrict the use in harsh environments especially in high temperature (>300 °C). SiC is a material, which allows exceeding these physical constraints. AMPERE laboratory have developed SiC integrated circuits based on lateral MESFETs. This paper presents the first steps of the development of smart integrated driver circuit dedicated to harsh environments.
The emerging 650 V large current rating, Enhancement-mode (E-mode) Gallium Nitride High-Electron-Mobility Transistor (GaN HEMT) is a promising device for low to medium power, high power density converters (e.g., motor drives, battery chargers), which require high robustness levels. Thus, a comprehensive study of the short circuit behavior of high power E-mode GaN HEMT is the subject of this paper...
To solve the simulation convergence problem of Silicon Carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) models, this paper proposes a non-segmented model for SiC MOSFETs, which uses non-segmented, smooth continuous equations to describe the static and dynamic characteristics of SiC MOSFET. Further, the static characteristic of SiC MOSFET obtained by the non-segmented model is...
This paper presents the development and validation of a physics-based compact model of IGCT for application in optimization of circuit parameters and GCT wafer design. The model proposed can simulate aspects of high-voltage IGCTs including impact ionization. It uses a Fourier series solution for the ambipolar diffusion equation in the base region. The model's simulation results are validated by comparision...
The single event transients (SETs) are a common source of malfunction in nano-scale CMOS integrated circuits. For this reason, evaluation of the SET effects and application of appropriate measures for their mitigation are fundamental tasks in the design of advanced radiation hardened integrated circuits. In general, SET analysis is based on the multi-scale modeling and simulation approach comprising...
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
This paper analyzes the sensitivity of five standard logic gates (AND, OR, INV, NAND and NOR) to Single Event Transients (SETs). All gates have been designed in IHP's 130 nm bulk CMOS technology. The analysis was conducted with SPICE simulations, employing the current injection concept to model the SET effects. The SET sensitivity of the investigated logic gates was evaluated in terms of critical...
Lateral GaN-on-Si HEMT technology enables integrated high-voltage half-bridges with gate drivers. However, the capacitive coupling through a common conductive substrate influences switching characteristics. The measured hard-switching turn-on time with floating substrate increased to over 16 ns as compared to conventional source-connected substrate (1 ns), switching 300 V/4A with GaN ICs comprising...
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