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Multi-core, Mixed Criticality Embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect...
Overheads due to context switching and external interrupt management are core characteristics for Real-Time Operating Systems (RTOS) since they play a central role in their performance and timeliness. In this paper we evaluate two core characteristics for the Real-Time Executive for Multiprocessor Systems (RTEMS), an operating system used for supporting space applications. Our assessment makes use...
Modern computing systems for vision have to support advanced image applications. They involve several heterogeneous pixel streams and they have to respect hard timing and area constraints. To face those challenges, an adaptable ring-based interconnection network-on-chip (NoC) has been recently proposed. This NoC is based on a new router architecture, with a dynamically adaptable internal datapath,...
In this paper, a MAC architecture designed by our institute based on high performance FPGA has been introduced. We also propose a firmware design scheme of the mobile support mechanism. Compared with other designs, the proposed structure improves the system integrated level and is easy for future enhancements. The implementation scheme of the mobile support mechanism in this paper can also be adopted...
The Red-Green light system is an important traffic control system, widely used in urban traffic management. Traffic light control systems need to achieve automatic control function at the junction changes. Traffic lights control system designed by single-chip computer work at a single mode, it is not easy to be upgraded or change device size. The reliability is low, slow and difficult to adapt the...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
The paper describes an original design of IEEE1149.1 testing bus controller IP core using reusable technology. We have designed the structure of IP core according to the function of IEEE1149.1 testing bus controller. Every function module of IP core was explained detailedly in this paper, including interface of microprocessor module, command control module, TMS creation module, TCK creation module...
This paper introduces novel circuits to mitigate power consumption in asynchronous logic. By exposing a preexisting timing assumption in quasi-delay insensitive (QDI) circuits, we develop a set of circuit templates that reduce dynamic power consumption while maintaining the robustness of QDI circuits. We refer to these as relaxed quasi delay-insensitive circuits (RQDI). Power consumption is reduced...
Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, the scope of this paper is to evaluate, on and for FPGA, the robustness of triple rail logic against power analyses. More precisely, this paper aims at demonstrating that the basic concepts on which leans this logic are valid and may provide interesting design guidelines to obtain DPA (differential...
Since FPGAs in future deep sub-micron processes will suffer from drastic speed and yield losses caused by device variations, we propose variation-aware reconfiguration that utilizes these variations for performance enhancement. To utilize random variations on a current deep submicron process for performance enhancement, optimizing each device from a common configuration is better than producing optimized...
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