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This paper proposes the service discovery and the remote control for Internet-of-Things (IoT) devices based on the Constrained Application Protocol (CoAP) and Domain Name System (DNS). As the number of devices increases, the manual configuration of domain names and services might be unmanageable for users. A legacy DNS Name Autoconfiguration (DNSNA) for IPv6 networks can be used to register the DNS...
Attacks on an operating system kernel using kernel rootkits pose a particularly serious threat. Detecting an attack is difficult when the operating system kernel is infected with a kernel rootkit. For this reason, handling an attack will be delayed causing an increase in the amount of damage done to a computer system. In this paper, we discuss KRGuard (Kernel Rootkits Guard), which is a new method...
Graphical device configuration tools are usually created statically from device description file. This description file specifies list of configurable registers, their descriptions and graphical controls. While this approach works well for simple controls modifying a single register, behavior of more complex controls needs to be described through script code. This paper presents a way of extending...
Register accuracy is an important index to evaluate the quality of printed electronic products. However, the complex relationships in multi-layer register system make the problem of decoupling control difficult to be solved. Hence, according to active disturbance rejection control (ADRC), a decoupling control strategy is proposed to improve precision and stability of the four-layer register system...
The approach to functional verification of communication controllers based on developing layered UVM test systems is considered in this paper. Some benefits of application standalone simulation based verification are marked out. The architecture most of communication controllers could be divided into three logical layers: the transport layer, the channel layer and the physical layer. The main features...
Parallel decoding of encoded data streams is an important scheme that is widely applied in image and video applications. Especially with the increasing demand on higher resolutions and frame rates, parallel decoding becomes very useful to meet the throughput requirements. Parallel decoding is conventionally enabled by inserting markers into the variable length code (VLC) stream. The markers allow...
At the heart of the European Rail Train Management System (ERTMS) is the European Train Control System (ETCS). One major goal of the ERTMS-ETCS project is the standardization and unification of all train control and command systems in Europe. Hence, it is critical to have a reliable test bed for ease of validation and certification, enforcing the reliability of ERTMS-ETCS train equipment. In this...
The authors developed an information measuring system which allows determining the dynamic behavior of the most relevant properties of a test object. This is an important aspect by choosing methods, tools and modes of vibration tests. The authors described block diagram model of the information measuring system and the test signal forming algorithm.
In built-in self-test (BIST), pseudo-random patterns generated by a linear feedback shift register (LFSR) are applied to a circuit under test as test patterns. Since random pattern resistant faults (RPRFs) exist, reseeding is used to detect them. In general, seeds that when expanded by the LFSR will produce test patterns for detecting RPRFs are used for reseeding. So far, we have proposed a one-pass...
In order to meet the requirements of communications devices in respect of data processing, display control and other aspects, this paper, on the basis of Core Connect bus that IBM proposes, designs and realizes a shared storage type SOPC parallel system by taking advantage of Xilinx's FPGA chip XC4VFX60 embedded two PPC405 processor hard-cores, which effectively improves the data processing capability...
Many algorithms have been design in order to accomplish an improved the performance of the filters by using the convolution design. The architecture of the proposed RISC CPU is a uniform 32-bit instruction format, single cycle non-pipelined processor. It has load/store architecture, where the operations will only be performed on registers, and not on memory locations. It follows the classical von-Neumann...
Our proposed architecture of dynamically reconfigurable hardware for protocol processing (DRHPP) provides flexibility with high area efficiency. It can be used for a communications system-on-a-chip (SoC) in access networks. The DRHPP enables the modification and addition of various functions for protocol processing. Our architecture consists of three types of cells. The optimized number of these types...
In the design of Fault Tolerant Systems, some type of hardware redundancy is often used, Triple Modular Redundancy being one of the well known techniques of this type. Anyway, it must be taken into account that, after one of the copies of the implemented hardware fails, then it loses fault mitigation ability and continues in operation degraded to self-checking pair. In today's dependable systems fault...
The IP multimedia subsystem (IMS) functionality is designed to work on a variety of wireless access technologies and in all network coverage such as macrocell, microcell and femtocell. In this paper we have implemented an IMS registration procedure for the LTE-based femtocell networks. Additionally, we proposed the SIP based IMS framework mechanism for LTE-based femtocell implementation. Two processes...
In this paper a communication solution for high demanding control systems is presented. The proposed solution is implemented in an FPGA where a control system for electric drives is realized. To create a useful project, the application was developed as open-code and furthermore, it can be implemented without costs for academic use.
The correctness of PLC (Programmable Logic Controller) program in automatic control is vital to this kind of safety-critical applications. In this paper, we present a useful method of combinational testing for correctness of PLC programs. The method is based on the denotational semantics of PLC program and the semantic functions for basic instructions. It establishes the definition of denotational...
In this work we present the fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing...
The MicroTCA.4 crate standard provides a powerful electronic platform for digital and analog signal processing. The crate standard is highly configurable and due to an excellent hardware modularity rapid adaption to various different applications is possible. Besides the hardware modularity, it is the software reliability and flexibility as well as the easy integration into existing software infrastructures...
We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-express bus on Altera Stratix 5 devices, using Direct Memory Access...
Versa Module Eurocard (VME) backplane bus based architecture has been standardized for Real Time Computer (RTC) based I&C systems of Indian fast reactors. A typical RTC consists of a CPU card and a set of I/O cards. VMEbus based CPU card is currently being used in the computer based I&C systems of FBTR at IGCAR. The CPU card uses a commercial VMEbus Interface controller (VIC), which is now...
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