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Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance. Except of fault-masking behavior and FPGA partial...
In the design of Fault Tolerant Systems, some type of hardware redundancy is often used, Triple Modular Redundancy being one of the well known techniques of this type. Anyway, it must be taken into account that, after one of the copies of the implemented hardware fails, then it loses fault mitigation ability and continues in operation degraded to self-checking pair. In today's dependable systems fault...
In last decades many techniques for fault tolerant system design in the field of reconfigurable hardware were presented. Some of them use the partial reconfiguration for the repair of component affected by the fault to extend the operational time of the system. The majority of these techniques is focused on transient fault mitigation which are more frequent. But the partial reconfiguration can be...
The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and...
In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting...
In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First, the principles of test platform based on an external SEU injector are presented; all components of test platform and their role during SEU simulation are described. Then, a recovery...
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