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This paper introduces a Maximum Gain Ring Oscillator (MGRO) topology that maximizes the power gain achieved by the active devices using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with guidelines for the design of the passive matching network. In the absence of passive losses, the topology can oscillate at the fmax...
This paper presents a new approach to design ultra low voltage fully-differential amplifiers, using CMOS inverter as a basic design element. With this technique, various circuit topologies, easily scalable to meet different constraints, were derived. Taking also the advantage of the full device control offered by a triple well technology, such amplifiers may be designed to operate at very low supply...
A low noise amplifier(LNA) working at GPS L1 band was designed using TSMC 0.18 μm CMOS process with inductively source-degeneration cascode topology. The design process was given firstly and then improved after considering the parasitics resulting from ESD protection circuit and package PAD. Simulation results show that the parasitic effects coming from ESD protection circuit and package PAD should...
In this paper, a 2.5GHz fully differential tuned LNA with integrated T/R switch is designed in a High-K metal gate 32nm digital CMOS process, and packaged in an SoC-compatible flip-chip package. Reliability constraints of the package severely limit the ability to depopulate soldering bumps, and RF components must be designed taking the bump location into account. The LNA achieves a 3.5dB NF, -5dBm...
In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused by the quantizer's input capacitance, while a local feedback loop compensates for the quantizer's excess delay. These meas ures allow a high-resolution multi-bit ΔΣ ADC to operate at GHz sampling rates. The bandwidth of this CMOS ΔΣ ADC is 6x wider than the state-of-the-art. Compared...
This work describes a 9bit 200MSPS 0.18μm CMOS process four-stage parallel pipeline ADC with 2.5 bit per stage. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated...
In this paper, a novel low-power current-reused folded cascode harmonic rejection mixer (HRM) for digital video broadcasting-terrestrial (DVB-T) tuner application is proposed. In proposed architecture, by adopting current-reused folded cascode topology, linearity of the HRM is improved and the low-power implementation is realized. In the frequency range of 48~862 MHz, simulation results of the proposed...
Many architectures of transistor only simulated inductors (TOSI) have been proposed until now in literature. Exhibiting tuning possibilities, low chip area and offering integration facility, they constitute promising architectures to replace passive inductors in RF circuits. An improved CMOS active inductor topology is proposed in this paper. With a novel loss compensation scheme, frequency increase...
In the future, CMOS technology is expected to enable low-cost sub-THz applications such as high data-rate communication links, passive and active imaging and sensor systems, and instrumentation and measurements equipment. This paper presents key design techniques for different CMOS LNA topologies with over 20 GHz bandwidth ranging from 90 GHz to 110 GHz. The proposed LNA topologies are, the three-stage...
This paper presents the design of a two-stage wide dynamic range variable gain amplifier (VGA). This is based on a new approximated exponential equation which offers a wide decibel linear range and an improved fully differential MOS Cherry-Hooper topology. In addition, the bandwidth of the VGA has been extended by using the capacitive neutralization technique for wide-band applications. Simulation...
This paper compares a new VLSI shifter topology based on an inverse butterfly network with a conventional barrel shifter using a structured custom CMOS design approach. The inverse butterfly network circuit is found to be larger and slower than a barrel shifter for both uni-directional and bi-directional rotations.
This paper deals with the implementation of full adder chains by mixing different CMOS full adder topologies. The proposed approach is based on cascading fast Gate Diffusion Input (GDI) Full Adders interrupted by static gate having driving capability, such as inverter, thus exploiting the intrinsic low power consumption of such topologies. The results obtained show that the proposed mixed-topology...
A 60-GHz injection-locked frequency divider (ILFD) fabricated in 65nm CMOS and operating at 1.2V consumes 1.65mW excluding buffers and biasing circuits, and has a measured locking range of 48.5-62.9GHz (25.9%) with 0dBm input power. The core ILFD area is 0.0157mm2. The large locking range is attributed to the use of the multi-order LC oscillator topology.
This paper describes a fully integrated 130nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. The measured receive path NF is 3.6~4.2, 4.2~4.7, and 5.4~6.2dB for the...
We present a novel fully differential input/output distributed transformer topology used for the design of millimeter-wave power amplifiers. Input/output distributed transformers are used to feed the input signal to four differential couples and to combine their output power. This topology improves the stability and the efficiency of the power amplifier, minimizing the chip area. The PA prototype...
A novel circuit topology for CMOS CML ring oscillators that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum frequency of the oscillator and maintains the same random jitter generation while greatly reducing the sinusoidal jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18μm...
This paper presents the concept and design of a wideband merged LNA and mixer covering the frequency range from 2GHz to 10GHz using a standard 0.18-μ m CMOS technology. Gm-boosting and current bleeding techniques are adopted to make the proposed single stage merged LNA and mixer topology suitable for high conversion gain, low noise and low power consumption operation. A proposed current peaking technique...
This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. A new topology to prevent the latch-up in single ended ring oscillators is proposed. The design is implemented in 0.18 μm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise...
A low-voltage high-gain double-balanced mixer for direct-conversion ultra-wideband (UWB) receiver based on CMOS 0.18 μm process is presented in this paper. The conversion gain of the proposed mixer is mainly boosted by current mirror technique and RF leakage-resonant technique. Measured results of the proposed mixer exhibit the conversion gain of 12.38 dB to 15.69 dB and the third-order intercept...
Energy efficient computation becomes increasingly important for battery driven ubiquitous computing applications. To extend the battery life time while still meeting the performance demands, the designers face critical challenges in choosing the appropriate circuit topologies and low-power design techniques in order to optimally balance the power and performance trade-offs. In this paper, we evaluate...
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