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We report on a 32-MHz quartz TCXO fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ± 0.2 ppm over temperature using on-chip third-order...
Warpage has become a very critical reliability problem for the advanced electronic packaging technique. One or more chips are stacked on the substrates for a device. The device thus contains materials that have different physical properties. The most prominent problem would be the differences in the thermal expansion coefficient for these materials. During fabrication, thermal energy was applied to...
Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We demonstrate a way to quantitatively measure the mechanical and kinetic behavior of an underfill epoxy resin containing a broad range of filler particles...
Thin film polymers play an essential role in system integration. The mechanical properties of the polymers are crucial for 3-D-Integration and advanced WLP because with the thinning of the silicon wafers, i.e. chips to less than 150 μm, the influence of the polymer layers gets an increasing impact on the mechanical stability of the electronic device. Next generation polymers have entered the market...
Experimental investigation for rapid thermal process (RTP) induced overlay residue was conducted. Silicon wafer substrate played a critical part in the RTP induced overlay residue. Substrates with epitaxial layers showed better overlay performance. High device densities tended to show worse overlay residue performance with same RTP process condition. Shallow trench isolation (STI) aspect ratio was...
NCA flip-chip bonding with thermoplastic elastomer adhesives is a new approach to connect surfaces - mostly with at least one flexible component - electrically and mechanically in one step. Although NCA bonding in general is a well-known process, so far only high-modulus thermosetting epoxy or acrylic adhesives are used. The application of thermoplastic elastomer adhesives identifies new opportunities...
This paper reports on the systematic characterization and modeling of a CMOS-based sensor for high-pressure applications. The sensor consists of an anodically bonded silicon-glass stack comprising an n-type Wheatstone bridge as the piezoresistive stress-sensing element. Surface trenches introduced into the silicon close to the Wheatstone bridge significantly increase the pressure sensitivity of the...
Due to high performance demand, the dimensions of chips should be reduced so the stacked 3D-ICs are introduced into semiconductor industry. For small substrate dimensions and high interconnects requirements, the FR-4 substrates are substituted by the Si substrates. The Si chips and substrates are thinned down. A rigid material like Si suffers much larger thermal stress when the thickness is below...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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