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This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis...
The partial reconfigurability of FPGAs allows real-time systems to adapt to changing application requirements. However, the additional time and power needed for partial reconfiguration as well as the sequential reconfiguration process degrade the overall system performance. This is considered as one of the main reasons for restricted use of partial reconfiguration technology. In addition, hardware...
In this paper, we propose a novel architecture to accelerate the Speeded Up Robust Features (SURF) algorithm by the use of configurable hardware. SURF is used in optical tracking systems to robustly detect distinguishable features within an image in a scale and rotation invariant way. In its performance critical part, SURF computes convolution filters at multiple scale levels without the need to create...
The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this paper...
The High-energy Stereoscopic System (H.E.S.S.) is an array of atmospheric Cherenkov telescopes dedicated to GeV-TeV γ ray astronomy. Four 12 meter diameter telescopes (CT) are currently in operation and a fifth 28 meter diameter telescope (LCT) should be completed by 2011. This will lower the system's energy threshold in stereoscopy down to ≈ 50 GeV. Concurrently, the LCT will also be used to detect...
In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII...
The multi-angle spectro-polarimetric imager (MSPI) is an advanced camera system under development at JPL for possible future consideration on a satellite based Aerosol-Cloud-Environment (ACE) mission as defined in the National Academies 2007 Decadal Survey. The MSPI project consists of three phases: Ground-MSPI, Air-MSPI, and Space-MSPI. Ground-MSPI is a ground-based demonstration focused on characterizing...
This paper presents the implementation of a face detection algorithm on FPGA for an eye mouse control system. An improved algorithm of skin color module and binary image projection is used to ensure real-time detection. The system is based on a hardware/software co-design, which consists of a dedicated hardware accelerator that solves the parts of the algorithm with higher computational cost and an...
Image filtering is mainly used for pre-processing in many applications of image processing such as noise removal in industrial inspection, enhancement for pattern recognition, restoration of degraded images, etc. For real-time processing, it is crucial that these applications meet the desired throughput. As processing demands get higher through complex algorithms and large resolution or very high...
The stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integrated circuits for maximum performance. This paper proposes a modified stable Euler-number based algorithm...
A critical step in fingerprint recognition is to skeletonize the fingerprint image for minutiae extraction, which is recognized as "thinning" in image processing. The speed and reliability of the thinning process are important for the whole fingerprint identification system. In this paper, to accelerate the thinning process, a fast hardware thinning algorithm is implemented on the Xilinx...
This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards - the sensor board, the USB board and the switch board - are used. As a verification method, 4-step verification strategy comprised...
Nowadays the real time video processing is becoming more and more critical. Thus the systems used for these purposes require powerful computation of the data in order to have short response time. Another attribute that is preferred for these systems to have, is versatility or offering the opportunity to be reconfigurable on demand. Co-design is a technique that involves both software and hardware...
SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation...
Self-organization is a natural concept that helps complex systems to adapt themselves autonomically to their environment. In this paper, we present a self-organizing framework for multi-cue fusion in embedded imaging. This means that several simple image filters are used in combination to lead to a more robust system behavior. Human motion tracking serves as a show case. The system adapts to changes...
In this paper, an FPGA-based design and implementation of a high-performance video processing platform (VPP) is presented. A hardware/software codesign system is proposed on Xilinx Virtex II Pro FPGA to realize complex algorithms for real-time image and video processing. This paper presents the framework of the VPP, discusses the architectural building blocks and FPGA synthesis results. Each hardware...
This paper presents the design methodology of hardware/software co-design on FPGA. In this research work uses line detection algorithm to be our case study. C-based programming named ImpulseC has been employed. By using this, we could reduce the time of the design. Two main components are involved. Edge detection module is the first component. Various algorithms, Robert, Sobel and Prewitt, are compared...
This paper proposes techniques for accelerating a software based image registration algorithm for 3D medical images targeting a reconfigurable hardware platform. Various methods, including dedicated fixed point arithmetic, error model based bit width analysis, architecture exploration and application-specific memory modules, are applied to address issues from the software algorithm and to maximize...
Watershed transformation is a powerful technique that can be efficiently used for image segmentation. In this paper, we implement a watershed based segmentation algorithm on a Virtex II Pro platform. The main contribution of this work is the low execution time and minimal internal FPGA consumed resources. The proposed architecture includes two main blocs. First, a gradient of the image is generated...
Current image sensors offer a raw output that incorporates a bayer color filter pattern, and additional processing is required to obtain a full color image. This paper presents a bilinear interpolation algorithm to demosaick images with bayer color pattern; the algorithm is implemented in a single field programmable gate array (FPGA) device using a pipelined architecture. A comparison between images...
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