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In this work, a simple electric circuit model for the evaluation of the impact of vias (inter-metallic vertical connections) in resonant rotary traveling wave oscillator (RTWO) is proposed. A test structure was designed to quantify the degradation on the signal integrity of RTWOs caused by these vias. The test structure and the RTWO were designed according to the rules of the 130 nm commercial mixed...
The single event transients (SETs) are a common source of malfunction in nano-scale CMOS integrated circuits. For this reason, evaluation of the SET effects and application of appropriate measures for their mitigation are fundamental tasks in the design of advanced radiation hardened integrated circuits. In general, SET analysis is based on the multi-scale modeling and simulation approach comprising...
This paper investigates the use of stacked depletion-mode n-channel MOSFET (D-MOS) for RF switch applications. Compared to the commonly used enhancement-mode MOSFET (E-MOS), the D-MOS transistor offers a significant reduction in on-state resistance (RON) and off-state capacitance (COFF) simultaneously and an excellent figure of merit (RonX Coff) of 134fs (roughly 3X improvement) can be achieved. With...
In order to improve the semiconductor device performance, decoupled plasma nitridation (DPN) process was used to form the ultra-thin gate oxide film. But we recently found serious residue defect on gate oxide film if we did lithography rework with chemical method. This defect was like a circular-pattern about several-micron in diameter and hard to be removed. The results also showed that the thickness...
In this paper, we propose a TFET (Tunneling Field Effect Transistor) PMU (power management unit) of R80515 for ultra-low power. Both the dynamic power and leakage power are evaluated by HSPICE circuit simulation with Verilog-A models. From the simulation, we find the dynamic power of TFET circuits can be reduced by 80% and leakage power reduction can be nearly 30% compared with 130nm CMOS (Complementary...
LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is widely used to smart power management IC, which can be attributed to its high operation voltage and high current driving capability. Furthermore, LDMOS is compatible with conventional CMOS processes. It will be much easier for IC foundries to make it by existing process flows. Operating at both a high drain voltage and a high current, LDMOS...
In this paper, we report that a nearly defect free In0.71Ga0.29As fin structure can be selectively grown inside oxide nano-trenches on a Ge template by using composition-graded InGaP as a buffer layer. A growth model is proposed to explain the strain energy accommodation behavior from Ge to In0.70Ga0.30P and then to In0.71Ga0.29As. This model offers a guideline for developing high quality high indium...
In this paper a Reliability-AwaRE (RARE) method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. The proposed method makes aging simulations on system level superfluous by utilizing a stochastic Look-Up table. The stochastic LUT contains simulated...
In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication...
We present a low-cost, portable electrochemical analysis system using impedimetric measurements rather than more commonly used potentiometric techniques. The presented impedance spectroscopy (impedimetric) technique uses a small perturbation to obtain a linearized response without affecting the composition of the sample as opposed to cyclic voltammetry (potentiometric) which repeatedly reduces and...
The main direction in the development of modern microelectronics is the improvement characteristics of electronic element base in the condition of the high temperature. The method of periodically doped channel is regarded as an application for transistor structures based on organic semiconductors. The possibility of channel conductivity modulation in CMOS transistors, however, is of high interest...
A substrate coupling analysis and simulation flow for high frequency CMOS system on chip design is presented. It's a straightforward method that can be directly adopted by designers as it only requires commercial design tools. Full chip level simulation including substrate, interconnect parasitics and package is provided in any stage of the design process. A 5 GHz CMOS LNA in the presence of an 88...
Throughout the last decade, the microprocessor industry has been struggling to preserve the benefits of Moore's Law scaling. The persistent scaling of CMOS technology no longer yields exponential performance gains due in part to the growth of dark silicon. With each subsequent technology node generation, power constraints resulting from factors such as sub-threshold leakage currents are projected...
We investigate the influence of additional dc current on response of CMOS THz detectors. A resistive self-mixing model calculation, shows that the voltage response of CMOS detectors increases significantly by applying a small dc current on the drain side of CMOS device. The calculation results are further verified by the experimental data from CMOS detectors at 0.65THz. The maximum voltage response...
Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay...
This paper demonstrates the design of analog circuits using simulated I/V data of a sample device (PMOS/NMOS), and estimation of transconductance (gm) from this plot using approximation. Proposed design technique is based on the fact that the ratio of transconductance (gm) is inversely proportional to the MOS gate-source voltage (VGs). From the amplifier specifications, bias current and the load (or...
This paper presents an approach to overt the cryptographic key, when there is any counter attacks so-called side-channel attacks (SCAs) are applied in order to break the security of AES-128. The algorithm was executed using ModelsimSE6.5e and various analyses were done in Xilinx 14.2 and MatLabR2014a. SCAs are based on examining the correlation produced between the data and operations performed by...
A hash map implementation of the link analysis technique for obtaining jitter is proposed, under non-linear receiver conditions. The jitter PDF obtained from the link analysis, which typically assumes an LTI system, is passed through the I/O non-linear CMOS receiver voltage characteristics, obtaining the final jitter distribution. Simulations show promising results.
In this paper, a 65-nm CMOS amplifier MMIC operating around 265 GHz is presented. To obtain a small signal gain of the amplifier in a frequency region close to Fmax (Maximum oscillation frequency) of a transistor, a neutralization technique of a feedback capacitance as well as a transistor model to neutralize it precisely are needed. For this purpose, the key is a de-embedding technique. To extract...
Current conveyors are widely used to implement current mode, voltage mode and mixed mode circuits of integer order. In this paper, a fractional order system is implemented using second generation current conveyor and a fractance device i.e. an RC network. The fractional order integrator of order half is designed for various s-domain models available in literature. The proposed integrators are realized...
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