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Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
The Keyed-Hash Message Authentication Codes(HMAC) is a useful mechanism for message authentication. In this paper, a high-performance HMAC/SHA-3 processor which can generate HMAC message digest and hash message digest is presented. Not only the standard length (224,256,384,512) of the message digest can be generated, but also a length of 64-bit message digest. Due to the application of new generation...
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and...
Enforcing the computer systems security policy is highly reliant upon the use of security monitors. The monitoring system should provide a complete view of the monitored system in a stealth mode. The Serial ATA Commands Logger system described in this paper intercepts the ATA commands sent by a host bus adapter to an attached storage device, by monitoring the exchanged traffic, in a transparent manner...
Network technology realizes ultra high speed digital data transmission system. FPGA based hardware controller can utilize this technology in the power electronics fields. Nano seconds order data transmission can be realized. In this paper, Rocket I/O protocol was applied to the FPGA based hardware controller, the network based high speed feedback implementation can be realized. 1MHz multi sampling...
This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the...
CAN FD (Controller Area Network with Flexible Data Rate) is a new standard which provides a fast data rate while preserving the compatibility with CAN. In this paper, we propose the C3 (Configurable CAN FD Controller) IP core architecture, which is compatible with the non-ISO CAN FD standard. C3 supports up to 96 transmit and receive buffers. The transmit buffers are organized as mailboxes with CAN...
Field Programmable Gate Arrays (FPGA) are becoming increasingly important in many digital systems due to their high performance and flexibility. The efficient utilization of programmable logic is still complex and requires in-depth knowledge. Therefore, understanding the basic principles of such devices and hardware description languages is of vital importance not only for students of electrical engineering...
Precise control of synchronous drive depends on the accurate position feedback of the rotor. This can be achieved using an absolute position encoder. One of the protocol used for encoder is Synchronous Serial Interface. The encoder with this protocol has to be interfaced with the drive or the testing setup in laboratory. In order to avoid a physical hardware, this paper proposes the SSI protocol implementation...
Several debugging methods are available for FPGA design, including logical simulation and physical debug. We face the challenge to systematize and apply a simple methodology using these methods to develop a communication processing module for a distributed control system with real time constraints. This methodology must follow some restrictions as to be easy to learn, use only available tools and...
This paper deals with hardware acceleration of statistical methods for detection of anomalies on 100Gb/s Ethernet. The approach is demonstrated by implementing a sequential Non-Parametric Cumulative Sum (NP-CUSUM) procedure. We use high-level synthesis in combination with emerging software defined monitoring (SDM) methodology for rapid development of FPGA-based hardware-accelerated network monitoring...
This paper proposed a platform for rapid prototyping of high-speed and low-power embedded applications in networking. The concept utilizes the FPGA with the embedded processor to benefit from software flexibility and high performance of hardware processing. In comparison with the NetFPGA-cube, the proposed uG4-150 platform has significantly lower power consumption, cost and size.
Most networking performance enhancements occur through specific static solutions, where the structure of the protocol stack remains unchanged. Instead, we focus on a flexible software and hardware co-design for the entire protocol stack. In this paper, we present EmbedNet, a System-on-Chip implementation of a flexible network architecture for the Future Internet, where parts of the protocol stack...
Software Defined Networking (SDN) has been described as the hope and hype for the future of networking. Definitions vary, but one research direction has been to separate the control plane from the data plane, introducing abstractions that can provide a global network view, a description of required behavior, and a model of packet forwarding. This is intended as a way to open up the closed-box and...
In access-network-chip testing and verification, problems occur mostly on I2C control interface because of its complicated protocol and high requirement on reliability, using an automated testing tool with simple operation and high testing coverage could ensure the quality of chip as well as shorten the chip development cycle. The paper designs an automated system based on 5SGXEA7N2F45C2 FPGA chip...
The ability of ultra-low latency to process market data feed is the premise and foundation for a today's trading system to grab the instant trading profits. The market data feed containing up-to-date information on market changes is multicasted real-timely from financial exchanges to market participants, usually in the form of financial information exchange (FIX) Adapted for STreaming (FAST) protocol...
In an effort to offset the rapidly increasing data volume processed by large data centers today, their architects have increasingly been exploring unconventional architectures like FPGAs. Large-scale RC systems like Novo-G# show promise for both big-data processing and HPC, but are limited by a lengthy and difficult design process. In this paper we present a mixed MPI/OpenCL framework that enables...
Direct Current (DC) line balanced SpaceWire is attractive for a number of reasons. Firstly, a DC line balanced interface provides the ability to isolate the physical layer with either a transformer or capacitor to achieve higher common mode voltage rejection and/or the complete galvanic isolation in the case of a transformer. Secondly, it provides the possibility to reduce the number of conductors...
In this paper, we propose a Controller Area Network with Flexible Data rate (CAN-FD) controller for communication network in automobile. The CAN FD is proper network protocol for in-vehicle and embedded communication which desires high reliability and data rate. We introduce our CAN FD controller which supports variable data length and faster data rate. The CAN FD controller receives data from virtual...
SOISOC3 is our new space-grade system-on-chip processor which is currently being developed by MHI in partnership with JAXA. The chip is implemented on a 200 nm radiation hardened process based on the commercial SOI (Silicon On Insulator), so that can apply to the Space missions. This is the next generation system-on-chip processor upgraded from the currentSOISOC2 chip already used for ASTRO-H, ERG...
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