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This paper presents the design and implementation of an incrementally scalable architecture for middleboxes based on commodity servers and operating systems. xOMB, the eXtensible Open MiddleBox, employs general programmable network processing pipelines, with user-defined C++ modules responsible for parsing, transforming, and forwarding network flows. We implement three processing pipelines in xOMB,...
Longest-prefix name-based forwarding in Content-Centric Networking poses many significant challenges on design of routers and algorithms, because the name space is many orders of magnitude larger and significantly more complex than the IP address space. IP forwarding algorithms are no longer applicable and cannot reach the satisfactory performance. In this paper, we present a framework of fast longest-name-prefix...
In Named Data Networking (NDN), forwarding lookup is based on tokenized variable-length names instead of fixed-length host addresses, and therefore it requires a new approach for designing a fast packet forwarding lookup engine. In this paper, we propose a design of an NDN software forwarding lookup engine based on hash tables and evaluate its performance with different design options. With a good...
These days, various academic and industrial institutions are sharing the computing resources of cloud data centers. For the sake of security, data center networks need to be separated by institution or department. One conventional approach is using tag-based VLAN standardized in IEEE 802.1Q. However, this approach cannot accommodate scalable networks because of a limitation on the number of VLAN IDs...
We propose the Floating Ground Architecture (FGA) for network mobility and ad hoc network convergence. Various factors, including excessive dependence on intelligence in the fixed network, result in the Internet having a de facto logical boundary one hop from the fixed network. To reduce these dependencies, FGA introduces a new logical layer, called Floating Ground, between the fixed network infrastructure...
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as...
Internet has witnessed its paramount function transition from host-to-host communication to content dissemination. Named Data Networking (NDN) and Content-Centric Networking (CCN) emerge as a clean slate network architecture to embrace this shift. Pending Interest Table (PIT) in NDN/CCN keeps track of the Interest packets that are received but yet un-responded, which brings NDN/CCN significant features,...
Content-Centric Networking (CCN) seeks to meet the content-centric needs of users. In this paper, we propose hybrid-COPSS, a hybrid content-centric architecture. We build on the previously proposed Content-Oriented Publish/Subscribe System (COPSS) to address incremental deployment of CCN and elegantly combine the functionality of content-centric networks with the efficiency of IP-based forwarding...
Network-based intrusion detection systems (NIDS) commonly use pattern languages to identify packets of interest. Similarly, security information and event management (SIEM) systems rely on pattern languages for real-time analysis of security alerts and event logs. Both NIDS and SIEM systems use pattern languages extended from regular expressions. One such extension, the submatch construct, allows...
This paper proposed a platform for rapid prototyping of high-speed and low-power embedded applications in networking. The concept utilizes the FPGA with the embedded processor to benefit from software flexibility and high performance of hardware processing. In comparison with the NetFPGA-cube, the proposed uG4-150 platform has significantly lower power consumption, cost and size.
Most networking performance enhancements occur through specific static solutions, where the structure of the protocol stack remains unchanged. Instead, we focus on a flexible software and hardware co-design for the entire protocol stack. In this paper, we present EmbedNet, a System-on-Chip implementation of a flexible network architecture for the Future Internet, where parts of the protocol stack...
Offloading has emerged as a promising idea to allow resource-constrained mobile devices to access intensive applications, without performance or energy costs, by leveraging external computing resources. This could be particularly useful in enterprise contexts where running line-of-business applications on mobile devices can enhance enterprise operations. However, we must address three practical roadblocks...
Table lookups and other types of packet processing require so much memory bandwidth that the networking industry has long been a major consumer of specialized memories like TCAMs. Extensive research in algorithms for longest prefix matching and packet classification has laid the foundation for lookup engines relying on area- and power-efficient random access memories. Motivated by costs and semiconductor...
The built-in caching capability of future Named Data Networking (NDN) promises to enable effective content distribution at a global scale without requiring special infrastructure. The aim of this work is to design efficient caching schemes in NDN to achieve better performance at both the network layer and application layer. With the specific objective of minimizing the inter-ISP (Internet Service...
The single-chip crosspoint-queued (CQ) switch is a self-sufficient switching architecture enabled by state-of-art ASIC technology. Unlike the legacy input-queued or output-queued switches, this kind of switch has all its buffers placed at the crosspoints of input and output lines. Scheduling is also performed inside the switching core, and does not rely on instantaneous communications with input or...
In this talk, I'll revisit the role of Software in Software-Defined Networking and argue how not only control plane but also forwarding is becoming increasingly only a matter of software development. In short, I'll discuss how x86 is already on its way to transform the networking as we know it.
The Data Vortex switch architecture provides promising routing performance with scalability but requires complicated connections as its size increases. The modular design is proposed that allows a larger network to be formed from smaller Data Vortex units for flexible implementations. Routing performance is shown to be similar or improved.
According to the specification of the OpenFlow protocol, whenever a flow table entry is absent for any arriving data packet, a packet-in message is sent to the controller. This behaviour results in various types of race conditions in accord with various packet and message orderings. Increased forwarding delay of data packets, increased complexity in performing software verification, and increased...
The system architecture of a network system is of fundamental importance to the performance of computer networks. However, evaluating different architectural and algorithmic choices of network systems is usually difficult. This poster presents NetSysSim, a network system simulator implemented in SystemC. NetSysSim provides a hierarchical framework of different levels of abstraction. With SystemC's...
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