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Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
Cyber-Physical Systems (CPS) are composed of computation, networking, and physical processes. Model-based design is a powerful technique to apply mathematical modeling in CPS design. A model of a physical system is the description of variations in some aspects and properties of the system such as motion, velocity, and pressure. The variations of physical quantities such as motion, velocity, and pressure...
Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because...
CNN involves large number of convolution of feature maps and kernels, necessary for extracting useful features for accurate classification. However, it requires significant amount of computationally intensive power and area hungry multiplications limiting its deployment on embedded devices under resource constrained scenario. To address this problem, we propose modified distributed arithmetic based...
In this paper a circuit-oriented approximate solution to an explicit nonlinear Model Predictive Control (NMPC) problem is proposed, based on piecewise-affine functions defined over simplicial domain partitions. The resulting controller is suitable for circuit implementation in programmable devices, such as microcontrollers or FPGA, enabling the application of NMPC to systems with low sampling times...
Digital Secret Unknown Cipher (SUC) has been proposed in the last decade targeting to counteract the drawbacks of the traditional analog Physical Unclonable Functions (PUF). The SUCs, as pure-digital units, exhibit consistent operation during the whole digital unit's lifetime. This makes SUCs as PUF alternatives attractive for practical creation of clone-resistant units for a broad spectrum of applications...
This paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DAΣ) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system...
Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly...
In recent years a wide range of wearable IoT healthcare applications have been developed and deployed. The rapid increase in wearable devices allows the transfer of patient personal information between different devices, at the same time personal health and wellness information of patients can be tracked and attacked. There are many techniques that are used for protecting patient information in medical...
Field-Programmable Gate Arrays (FPGAs) provide highly flexible platforms to implement sophisticated data processing for scientific space instruments. The dynamic partial reconfiguration (DPR) capability of FPGAs allows it to schedule HW tasks. While this feature adds another dimension of processing power that can be exploited without significantly increasing system complexity and power consumption,...
We demonstrate real-time CD equalization (CDE) for coherent optical transmission systems using a low complexity time-domain (TD) multiplierless finite-impulse response (FIR)-based equalizer, based on a field-programmable gate array (FPGA) implementation. The real-time operation is performed for a single-channel 2.5 Gb/s QPSK optical signal with a performance penalty of only ∼0.15 dB with respect to...
In recent years, there has been a dramatic increase in utilization of FPGAs to enhance the speed-performance of many real-time compute and data intensive applications on embedded platforms. FPGA-based designs leverage parallelism in computations to achieve high speed-performance. Parallel computations require multi-ported memories to provide any number of ports for simultaneous multiple read/write...
State-of-the-art CNN models for Image recognition use deep networks with small filters instead of shallow networks with large filters, because the former requires fewer weights. In the light of above trend, we present a fast and efficient FPGA based convolution engine to accelerate CNN models over small filters. The convolution engine implements Winograd minimal filtering algorithm to reduce the number...
In wireless vehicular communication, channel properties change rapidly over time. Both, the transmitter and the receiver, are moving, which generates not only time and frequency (doubly) selective channels but also channel statistics that are non-stationary, i.e., they change over time. New wireless vehicular communication systems for connected autonomous vehicles require validation and verification...
In this paper we propose and investigate some simplifications to the original Histogram of Oriented Gradients (HOG) algorithm, in order to allow a more efficient hardware implementation, while keeping the overall classification accuracy. The most aggressive simplification is the removal of the bin interpolation step in the algorithm, which does not affect the classification performance, but significantly...
In recent years, the information technology world have faced broad security issues due to the large amount of data flowing over the network. HW security solutions are often preferred in contexts where an high level of performance is required. Multiple HW implementation of the Advanced Encryption Standard can be found in literature. Although several optimization methods based on optimum composite field...
Massive multiple-input multiple-output (massive MIMO) system or so-called large scale antenna system (LSAS) has been identified as one of the promising candidates for 5G wireless communications systems. In general, a massive MIMO architecture can be split into two main parts, the massive MIMO baseband digital platform and the massive MIMO radio platform. Although several studies have been already...
Polar code has become a major milestone in information theory field in recent times. Researchers are still observing more efficient encoding and decoding structures. In this study, a new WIB based structure is proposed which reduces the computational complexity of WIB introduced as an early termination method for BP polar decoder in literature. Both proposed and WIB methods are implemented with VHDL...
This work is focused on FPGA based implementations of the SHA-3 hash functions. The existing literature classifies the existing implementations according to the adopted structural optimization techniques, namely: folding, pipelining and unrolling. Several structures have been proposed in the state-of-the-art, which vary mainly in the level of folding and the number of pipeline stages. While unfolded...
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